Dejan Marko Markovic

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-65

May 18, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-65.pdf

The complexity of integrated circuits (ICs) in wireless communication devices has been steadily increasing to support more functionality and new ideas from information theory. Computational requirements can be quite drastic, especially in multi-antenna (MIMO) communication systems which use multi-dimensional signal processing algorithms. The required increase in computational efficiency in MIMO systems can be far greater than the improvements provided by scaling of IC technology alone.

This work will present a methodology for power/area efficient ASIC realization of signal processing algorithms for wireless communications, taking into account unique features of scaled technology such as leakage power and process variation. A sensitivity based optimization framework will be applied to multiple layers of design abstraction: circuits, micro-architecture, and macro-architecture. The proposed approach enables power and area optimizations across the boundary of algorithm, architecture, and circuits, which is essential for creating globally optimal designs.

In wireless baseband chip realization, the design cycle traditionally requires reentering data at various abstraction levels, thus constraining the implementation choices and increasing time-to-market. An approach using a unified design description for algorithm verification and architecture exploration is also presented. The proposed graphical block-based design entry and retargetable design flow provide the ability to track technology features in the process of architectural selection.

As a proof of concept, the design methodology will be demonstrated on a wideband 4x4 MIMO channel decoupling through singular value decomposition. The computational throughput of 70GOPS was implemented with 0.5 million gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. The chip achieves a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a standard 90nm CMOS process.

Advisors: Robert W. Brodersen and Borivoje Nikolic

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BibTeX citation:

@phdthesis{Markovic:EECS-2006-65,
    Author= {Markovic, Dejan Marko},
    Title= {A Power/Area Optimal Approach to VLSI Signal Processing},
    School= {EECS Department, University of California, Berkeley},
    Year= {2006},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-65.html},
    Number= {UCB/EECS-2006-65},
    Abstract= {The complexity of integrated circuits (ICs) in wireless communication devices has been steadily increasing to support more functionality and new ideas from information theory.  Computational requirements can be quite drastic, especially in multi-antenna (MIMO) communication systems which use multi-dimensional signal processing algorithms.  The required increase in computational efficiency in MIMO systems can be far greater than the improvements provided by scaling of IC technology alone.

This work will present a methodology for power/area efficient ASIC realization of signal processing algorithms for wireless communications, taking into account unique features of scaled technology such as leakage power and process variation.  A sensitivity based optimization framework will be applied to multiple layers of design abstraction: circuits, micro-architecture, and macro-architecture.  The proposed approach enables power and area optimizations across the boundary of algorithm, architecture, and circuits, which is essential for creating globally optimal designs.

In wireless baseband chip realization, the design cycle traditionally requires reentering data at various abstraction levels, thus constraining the implementation choices and increasing time-to-market.  An approach using a unified design description for algorithm verification and architecture exploration is also presented.  The proposed graphical block-based design entry and retargetable design flow provide the ability to track technology features in the process of architectural selection.

As a proof of concept, the design methodology will be demonstrated on a wideband 4x4 MIMO channel decoupling through singular value decomposition.  The computational throughput of 70GOPS was implemented with 0.5 million gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. The chip achieves a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a standard 90nm CMOS process.},
}

EndNote citation:

%0 Thesis
%A Markovic, Dejan Marko 
%T A Power/Area Optimal Approach to VLSI Signal Processing
%I EECS Department, University of California, Berkeley
%D 2006
%8 May 18
%@ UCB/EECS-2006-65
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-65.html
%F Markovic:EECS-2006-65