Varadarajan Vidya

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2007-51

May 9, 2007

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-51.pdf

Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alternate transistor architectures such as the planar ultra-thin body (UTB) FET and double-gate MOSFET may be necessary to continue gate length scaling down to the sub-10nm regime. The non-planar FinFET is perhaps the most promising double-gate structure for integrated circuit manufacture. However, some key fabrication issues that are yet to be resolved include super-steep source/drain junction formation with high uniformity and dual metal gate technology with work function engineering for dense layouts. Furthermore, statistical variations due to factors such as dopant fluctuation effects and line-edge roughness demand the need for variation-tolerant device and circuit designs. One way to tackle the challenges in the formation of uniform and steep source/drain junctions in FinFETs is to completely eliminate all p-n junctions in the device. By having the source/drain and channel regions of the same doping type, the device can be operated in accumulation mode instead of inversion mode. It is found that this architecture shows comparable intrinsic delay and lower gate leakage compared to the enhancement mode FinFET, but higher sensitivity to process variations. Single gate work function CMOSFET design is studied to make metal gate technology more practical for FinFETs. It is shown that high performance, low standby power, and low operating power CMOS can be implemented by utilizing the electrical channel length (Leff) as a VT tuning variable, where, Leff is optimized through an optimum choice of side-wall spacer thickness (LSP) and source/drain gradient abruptness (SD). In this methodology, Leff and silicon fin thickness (TSi) are the only optimization variables and a tradeoff between performance and variability is inherent to this device design scheme. Through 3D atomistic simulations, it is identified that lean spacers and steep junctions, along with a relatively thick TSi will be necessary to minimize variations. The concept of thin-body MOSFETs is extended to three-dimensional integration through a novel, low thermal budget, cost-effective integration methodology. Unlike conventional techniques, the proposed method focuses on building FETs directly within interconnect wires. The technique has been demonstrated on the aluminum-silicon system using the concept of aluminum induced crystallization of silicon.

Advisors: Tsu-Jae King Liu

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BibTeX citation:

@phdthesis{Vidya:EECS-2007-51,
    Author= {Vidya, Varadarajan},
    Title= {Thin-Body Silicon FET Devices and Technology},
    School= {EECS Department, University of California, Berkeley},
    Year= {2007},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-51.html},
    Number= {UCB/EECS-2007-51},
    Abstract= {Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alternate transistor architectures such as the planar ultra-thin body (UTB) FET and double-gate MOSFET may be necessary to continue gate length scaling down to the sub-10nm regime. 
The non-planar FinFET is perhaps the most promising double-gate structure for integrated circuit manufacture. However, some key fabrication issues that are yet to be resolved include super-steep source/drain junction formation with high uniformity and dual metal gate technology with work function engineering for dense layouts. Furthermore, statistical variations due to factors such as dopant fluctuation effects and line-edge roughness demand the need for variation-tolerant device and circuit designs.
One way to tackle the challenges in the formation of uniform and steep source/drain junctions in FinFETs is to completely eliminate all p-n junctions in the device. By having the source/drain and channel regions of the same doping type, the device can be operated in accumulation mode instead of inversion mode. It is found that this architecture shows comparable intrinsic delay and lower gate leakage compared to the enhancement mode FinFET, but higher sensitivity to process variations. 
Single gate work function CMOSFET design is studied to make metal gate technology more practical for FinFETs. It is shown that high performance, low standby power, and low operating power CMOS can be implemented by utilizing the electrical channel length (Leff) as a VT tuning variable, where, Leff is optimized through an optimum choice of side-wall spacer thickness (LSP) and source/drain gradient abruptness (SD). In this methodology, Leff and silicon fin thickness (TSi) are the only optimization variables and a tradeoff between performance and variability is inherent to this device design scheme. Through 3D atomistic simulations, it is identified that lean spacers and steep junctions, along with a relatively thick TSi will be necessary to minimize variations.
The concept of thin-body MOSFETs is extended to three-dimensional integration through a novel, low thermal budget, cost-effective integration methodology. Unlike conventional techniques, the proposed method focuses on building FETs directly within interconnect wires. The technique has been demonstrated on the aluminum-silicon system using the concept of aluminum induced crystallization of silicon.},
}

EndNote citation:

%0 Thesis
%A Vidya, Varadarajan 
%T Thin-Body Silicon FET Devices and Technology
%I EECS Department, University of California, Berkeley
%D 2007
%8 May 9
%@ UCB/EECS-2007-51
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-51.html
%F Vidya:EECS-2007-51