Mark Whitney

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2009-80

May 21, 2009

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-80.pdf

Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.

We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.

Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor’s factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor’s algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.

Advisors: John D. Kubiatowicz

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BibTeX citation:

@phdthesis{Whitney:EECS-2009-80,
    Author= {Whitney, Mark},
    Title= {Practical Fault Tolerance for Quantum Circuits},
    School= {EECS Department, University of California, Berkeley},
    Year= {2009},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-80.html},
    Number= {UCB/EECS-2009-80},
    Abstract= {Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.

We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.

Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor’s factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product.
Additionally, the area of our layout of a 1024-bit factoring using Shor’s algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work.  A design size reduction by this amount will make fabricating such an application feasible much sooner.},
}

EndNote citation:

%0 Thesis
%A Whitney, Mark 
%T Practical Fault Tolerance for Quantum Circuits
%I EECS Department, University of California, Berkeley
%D 2009
%8 May 21
%@ UCB/EECS-2009-80
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-80.html
%F Whitney:EECS-2009-80