Huy Vo

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2013-98

May 17, 2013

This thesis classifies Chisel hardware construction into three levels. At the first level, users write Chisel code at the granularity of nodes. The second level of hardware construction uses functional abstraction to group nodes into subgraphs. To illustrate the differences between these levels, we show how someone would implement a new hardware facility at both levels of hardware construction. At the third level of hardware construction, users write elaboration time function that the Chisel compiler invokes on the user’s behalf to construct hardware. We present three examples of writing elaboration time functions to build hardware.

Advisors: Krste Asanović

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BibTeX citation:

@mastersthesis{Vo:EECS-2013-98,
    Author= {Vo, Huy},
    Title= {Hardware Construction in Chisel},
    School= {EECS Department, University of California, Berkeley},
    Year= {2013},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-98.html},
    Number= {UCB/EECS-2013-98},
    Abstract= {This thesis classifies Chisel hardware construction into three levels. At the first level, users
write Chisel code at the granularity of nodes. The second level of hardware construction uses
functional abstraction to group nodes into subgraphs. To illustrate the differences between
these levels, we show how someone would implement a new hardware facility at both levels
of hardware construction. At the third level of hardware construction, users write elaboration
time function that the Chisel compiler invokes on the user’s behalf to construct hardware. We
present three examples of writing elaboration time functions to build hardware.},
}

EndNote citation:

%0 Thesis
%A Vo, Huy 
%T Hardware Construction in Chisel
%I EECS Department, University of California, Berkeley
%D 2013
%8 May 17
%@ UCB/EECS-2013-98
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-98.html
%F Vo:EECS-2013-98