Yale Chen and Bhavana Chaurasia and Ian Juch and Surabhi Kumar and Jay Mistry

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2015-93

May 14, 2015

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-93.pdf

Because of physical limitations on how fast we can operate modern digital integrated circuits, trends point towards increasing the number of processing cores by leveraging parallelism. Fast and efficient communication between all of these cores is paramount for optimal performance. In our report, we explore the design space of high radix switches up to 64x64 ports. We also examine alternative methods of building the switch using Synopsys design tools.

Advisors: Elad Alon and Vladimir Stojanovic

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BibTeX citation:

@mastersthesis{Chen:EECS-2015-93,
    Author= {Chen, Yale and Chaurasia, Bhavana and Juch, Ian and Kumar, Surabhi and Mistry, Jay},
    Title= {Petabit Switch Fabric Design},
    School= {EECS Department, University of California, Berkeley},
    Year= {2015},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-93.html},
    Number= {UCB/EECS-2015-93},
    Abstract= {Because of physical limitations on how fast we can operate modern digital integrated circuits, trends point towards increasing the number of processing cores by leveraging parallelism. Fast and efficient communication between all of these cores is paramount for optimal performance. In our report, we explore the design space of high radix switches up to 64x64 ports. We also examine alternative methods of building the switch using Synopsys design tools.},
}

EndNote citation:

%0 Thesis
%A Chen, Yale 
%A Chaurasia, Bhavana 
%A Juch, Ian 
%A Kumar, Surabhi 
%A Mistry, Jay 
%T Petabit Switch Fabric Design
%I EECS Department, University of California, Berkeley
%D 2015
%8 May 14
%@ UCB/EECS-2015-93
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-93.html
%F Chen:EECS-2015-93