Korok Chatterjee

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2018-131

September 4, 2018

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-131.pdf

Because of the thermal distribution of electrons in a semiconductor, modern transistors cannot be turned on more sharply than 60 mV of gate voltage for an order of magnitude increase in drain current, the so-called ”Boltzmann tyranny.” This results in an inability to reduce supply voltage, increasing power dissipation in advanced complementary metal- oxide-semiconductor (CMOS) technologies, which threatens the continuation of exponential transistor scaling, also known as Moore’s Law. For this reason, there has been a push in the device research community to invent novel steep swing devices. Negative capacitance in ferroelectric materials was proposed in 2008 by Salahuddin and Datta to provide voltage amplification without needing to design a totally new device. A negative gate capacitance would step-up the applied gate voltage at the semiconductor channel, causing the surface potential to rise faster than the gate voltage, lowering the subthreshold slope below 60 mV/decade. In this work, we attempt to characterize the charge-voltage characteristics of ferroelectrics biased into the negative capacitance regime. Although negative capacitance was experimentally demonstrated in 2010, significant challenges have remained to the practical realization of negative capacitance field-effect transistors (FETs). First, we investigate negative capacitance in an isolated ferroelectric capacitor, and show that the negative capacitance states can be directly observed during switching. Careful analysis of the switching dynamics and phase-field modeling show that the signature of negative capacitance arises from the accelerating growth of domain walls, when an increasing volume fraction of the ferroelectric is depolarized. Although this offers insight into the origins of negative capacitance and help to establish its existence scientifically, it does not address the problem of design. A primary concern is the speed of polarization response, which should be on the order of 1 picosecond or less in order to maintain circuit performance. By analyzing the electromagnetic absorption spectrum of hafnium oxide, the primary candidate for CMOS integration, we are able to estimate the intrinsic delay time as being on the order of 270 fs. Next, in order to maximize the amplification and provide adequate margins for hysteresis-free operation, it is necessary to understand how coupling of the ferroelectric material to the interfacial oxide and semiconductor affects its behavior, and to be able to predict what values of negative capacitance will be realized for a certain material and geometry. This is the problem of capacitance matching, which we aim to solve by using the underlying transistor itself as a charge sensor. By calibrating the drain current to the surface potential in reference devices, we may ascertain the characteristics of the ferroelectric in the negative capacitance devices. This is first carried out with an epitaxial ferroelectric capacitor externally connected to the gate of pre-fabricated Fin-FETs. Following this, we describe the development of an in-house fabrication process using silicon-on-insulator substrates, which allows for simple and efficient process flows. Then, we describe the characterization of these devices, including quasistatic and low-frequency current-voltage (I-V) and capacitance voltage (C-V) measurements, a fast pulse-gated I-V measurement, and an excursion into the memory characteristics of our fabricated FETs. Finally, we discuss efforts to build a computational model of our devices from which we can extract the ferroelectric characteristics needed for predictive design.

Advisors: Sayeef Salahuddin

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BibTeX citation:

@phdthesis{Chatterjee:EECS-2018-131,
    Author= {Chatterjee, Korok},
    Editor= {Salahuddin, Sayeef and Hu, Chenming and Ramesh, Ramamoorthy},
    Title= {Design and Characterization of Ferroelectric Negative Capacitance},
    School= {EECS Department, University of California, Berkeley},
    Year= {2018},
    Month= {Sep},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-131.html},
    Number= {UCB/EECS-2018-131},
    Abstract= {Because of the thermal distribution of electrons in a semiconductor, modern transistors cannot be turned on more sharply than 60 mV of gate voltage for an order of magnitude increase in drain current, the so-called ”Boltzmann tyranny.” This results in an inability to reduce supply voltage, increasing power dissipation in advanced complementary metal- oxide-semiconductor (CMOS) technologies, which threatens the continuation of exponential transistor scaling, also known as Moore’s Law. For this reason, there has been a push in the device research community to invent novel steep swing devices. Negative capacitance in ferroelectric materials was proposed in 2008 by Salahuddin and Datta to provide voltage amplification without needing to design a totally new device. A negative gate capacitance would step-up the applied gate voltage at the semiconductor channel, causing the surface potential to rise faster than the gate voltage, lowering the subthreshold slope below 60 mV/decade. In this work, we attempt to characterize the charge-voltage characteristics of ferroelectrics biased into the negative capacitance regime. Although negative capacitance was experimentally demonstrated in 2010, significant challenges have remained to the practical realization of negative capacitance field-effect transistors (FETs).
First, we investigate negative capacitance in an isolated ferroelectric capacitor, and show that the negative capacitance states can be directly observed during switching. Careful analysis of the switching dynamics and phase-field modeling show that the signature of negative capacitance arises from the accelerating growth of domain walls, when an increasing volume fraction of the ferroelectric is depolarized. Although this offers insight into the origins of negative capacitance and help to establish its existence scientifically, it does not address the problem of design. A primary concern is the speed of polarization response, which should be on the order of 1 picosecond or less in order to maintain circuit performance. By analyzing the electromagnetic absorption spectrum of hafnium oxide, the primary candidate for CMOS integration, we are able to estimate the intrinsic delay time as being on the order of 270 fs. Next, in order to maximize the amplification and provide adequate margins for hysteresis-free operation, it is necessary to understand how coupling of the ferroelectric material to the interfacial oxide and semiconductor affects its behavior, and to be able to predict what values of negative capacitance will be realized for a certain material and geometry. This is the problem of capacitance matching, which we aim to solve by using the underlying transistor itself as a charge sensor. By calibrating the drain current to the surface potential in reference devices, we may ascertain the characteristics of the ferroelectric in the negative capacitance devices. This is first carried out with an epitaxial ferroelectric capacitor externally connected to the gate of pre-fabricated Fin-FETs. Following this, we describe the development of an in-house fabrication process using silicon-on-insulator substrates, which allows for simple and efficient process flows. Then, we describe the characterization of these devices, including quasistatic and low-frequency current-voltage (I-V) and capacitance voltage (C-V) measurements, a fast pulse-gated I-V measurement, and an excursion into the memory characteristics of our fabricated FETs. Finally, we discuss efforts to build a computational model of our devices from which we can extract the ferroelectric characteristics needed for predictive design.},
}

EndNote citation:

%0 Thesis
%A Chatterjee, Korok 
%E Salahuddin, Sayeef 
%E Hu, Chenming 
%E Ramesh, Ramamoorthy 
%T Design and Characterization of Ferroelectric Negative Capacitance
%I EECS Department, University of California, Berkeley
%D 2018
%8 September 4
%@ UCB/EECS-2018-131
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-131.html
%F Chatterjee:EECS-2018-131