Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design

Juan Duarte

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2018-24
May 2, 2018

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-24.pdf

Mathematical compact models play a key role in designing integrated circuits. They serve as a medium of information exchange between foundries and designers. A compact model, which is a set of long mathematical equations based on the physics of each transistor, is capable of reproducing the very complex transistor characteristics in an accurately, fast, and robust manner. This dissertation presents the latest research on compact models for advanced transistor technologies: FinFETs, Ultra-thin body SOIs (UTBSOIs), Gate-All-Around (GAA) FETs, and Negative Capacitance (NC) FETs.

Since traditional transistor scaling had reached limitations due short-channel effects and oxide tunneling, the introduction of FinFET and UTBSOIs in high-volume manufacturing at 20nm, 14nm and 10nm technology nodes had let the electronic industry to keep obtaining performance and density advantages in technology scaling. For smaller nodes such as 5nm, and 3nm, GAA FETs transistors are expected to replace traditional transistors. Production ready compact model for current and future FinFETs are presented in this thesis. The Unified Compact Model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. A new quantum effects model will also be presented, it enables accurate modeling of III-V FinFETs. Shape agnostic short-channel effect model for aggressive LG scaling and body bias model for FinFETs on bulk substrates are also included in this work. This computationally efficient model is an ideal turn-key solution for simulation and design of future heterogeneous circuits.

For extremely scaled technologies, NC-FETs are quickly emerging as preferred candidates for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has led to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.

This thesis gives insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in commercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping to minimize the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, VDD scaling becomes more dominant on energy reduction of NC-FinFET based circuits.

Advisor: Chenming Hu


BibTeX citation:

@phdthesis{Duarte:EECS-2018-24,
    Author = {Duarte, Juan},
    Title = {Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design},
    School = {EECS Department, University of California, Berkeley},
    Year = {2018},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-24.html},
    Number = {UCB/EECS-2018-24},
    Abstract = {Mathematical compact models play a key role in designing integrated circuits. They serve as a medium of information exchange between foundries and designers. A compact model, which is a set of long mathematical equations based on the physics of each transistor, is capable of reproducing the very complex transistor characteristics in an accurately, fast, and robust manner. This dissertation presents the latest research on compact models for advanced transistor technologies: FinFETs, Ultra-thin body SOIs (UTBSOIs), Gate-All-Around (GAA) FETs, and Negative Capacitance (NC) FETs. 

Since traditional transistor scaling had reached limitations due short-channel effects and oxide tunneling, the introduction of FinFET and UTBSOIs in high-volume manufacturing at 20nm, 14nm and 10nm technology nodes had let the electronic industry to keep obtaining performance and density advantages in technology scaling. For smaller nodes such as 5nm, and 3nm, GAA FETs transistors are expected to replace traditional transistors. Production ready compact model for current and future FinFETs are presented in this thesis. The Unified Compact Model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. A new quantum effects model will also be presented, it enables accurate modeling of III-V FinFETs. Shape agnostic short-channel effect model for aggressive LG scaling and body bias model for FinFETs on bulk substrates are also included in this work. This computationally efficient model is an ideal turn-key solution for simulation and design of future heterogeneous circuits. 

For extremely scaled technologies, NC-FETs are quickly emerging as preferred candidates for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has led to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.

This thesis gives insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in commercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping to minimize the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, VDD scaling becomes more dominant on energy reduction of NC-FinFET based circuits.}
}

EndNote citation:

%0 Thesis
%A Duarte, Juan
%T Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design
%I EECS Department, University of California, Berkeley
%D 2018
%8 May 2
%@ UCB/EECS-2018-24
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-24.html
%F Duarte:EECS-2018-24