Edward Wang

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2020-28

May 1, 2020

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-28.pdf

Why is it still so difficult to tape out a chip even when an organization has taped out many chips before? Physical design is necessary to tape out a realistic chip, but often solutions are not encoded in a re-usable way, resulting in time wasted in solving repeated software/logistics problems. Existing attempts such as ad-hoc scripts, inline attributes, non-modular, and monolithic flows inhibit capturing and encoding physical design information in a re-usable manner. Previous agile design tools like Chisel, FIRRTL, and BAG do well to enable agile chip building, but their effectiveness is limited since those tools don’t address digital physical design, turning physical design into a bottleneck. To enable rapid ASIC development and facilitate re-use in VLSI/physical design, we present an agile physical design methodology consisting of a physical design IR, library abstractions for tools/technologies, and framework-style drivers and shell wrappers to make it easy to start using the abstraction libraries and agile hardware transforms/DSLs to generate physical design information in lockstep. The methodology is incremental and backwards-compatible, allowing designers to progressively adopt it and revert to underlying technologies (in 28nm and 16nm) to solve unaddressed problems or build new use cases. We test our methodology on two tapeouts and explore possible benefits in re-use and time to minimal viable product.

Advisors: Jonathan Bachrach

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BibTeX citation:

@mastersthesis{Wang:EECS-2020-28,
    Author= {Wang, Edward},
    Title= {HAMMER: A Platform For Agile Physical Design},
    School= {EECS Department, University of California, Berkeley},
    Year= {2020},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-28.html},
    Number= {UCB/EECS-2020-28},
    Abstract= {Why is it still so difficult to tape out a chip even when an organization has taped out
many chips before? Physical design is necessary to tape out a realistic chip, but often
solutions are not encoded in a re-usable way, resulting in time wasted in solving repeated
software/logistics problems. Existing attempts such as ad-hoc scripts, inline attributes,
non-modular, and monolithic flows inhibit capturing and encoding physical design
information in a re-usable manner. Previous agile design tools like Chisel, FIRRTL, and
BAG do well to enable agile chip building, but their effectiveness is limited since those
tools don’t address digital physical design, turning physical design into a bottleneck.
To enable rapid ASIC development and facilitate re-use in VLSI/physical design, we
present an agile physical design methodology consisting of a physical design IR, library
abstractions for tools/technologies, and framework-style drivers and shell wrappers to
make it easy to start using the abstraction libraries and agile hardware transforms/DSLs
to generate physical design information in lockstep. The methodology is incremental
and backwards-compatible, allowing designers to progressively adopt it and revert to
underlying technologies (in 28nm and 16nm) to solve unaddressed problems or build
new use cases. We test our methodology on two tapeouts and explore possible benefits
in re-use and time to minimal viable product.},
}

EndNote citation:

%0 Thesis
%A Wang, Edward 
%T HAMMER: A Platform For Agile Physical Design
%I EECS Department, University of California, Berkeley
%D 2020
%8 May 1
%@ UCB/EECS-2020-28
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-28.html
%F Wang:EECS-2020-28