Yuan-Cheng Tsai

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2021-132

May 15, 2021

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-132.pdf

As Chipyard (Berkeley's open-source SoC development framework) and Chisel (Berkeley's open-source hardware description language) are rapidly growing in popularity within both academia and industry, the need of a compatible verification library is stronger than ever. The industry standard UVM is not suitable with Chisel circuits, as although the generated Verilog can be verified, readability and debuggability is challenging for large designs. Moreover, as Chisel is built upon Scala, a general multi-purpose programming language, special high-level constructs such as type classes and generics that Chisel circuits are parameterized by are very difficult to represent in SystemVerilog. The open-source Chisel Verification Library remedies this disconnect between Chisel and UVM by providing high level verification constructs for Chisel testbenches. It is modeled off of UVM to contain the benefits of the test component abstractions such as the driver and monitor, and it also supports common interfaces such as the Decoupled and TileLink interface. Moreover, the library includes a SVA-like specification language eDSL that enable users to write property assertions on output traces. The library has been used in several applications, such as the verification of a RAM module, L2 cache, as well as an AES cryptography accelerator.

Advisors: Borivoje Nikolic

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BibTeX citation:

@mastersthesis{Tsai:EECS-2021-132,
    Author= {Tsai, Yuan-Cheng},
    Title= {Dynamic Verification Library for Chisel},
    School= {EECS Department, University of California, Berkeley},
    Year= {2021},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-132.html},
    Number= {UCB/EECS-2021-132},
    Abstract= {As Chipyard (Berkeley's open-source SoC development framework) and Chisel (Berkeley's open-source hardware description language) are rapidly growing in popularity within both academia and industry, the need of a compatible verification library is stronger than ever. The industry standard UVM is not suitable with Chisel circuits, as although the generated Verilog can be verified, readability and debuggability is challenging for large designs. Moreover, as Chisel is built upon Scala, a general multi-purpose programming language, special high-level constructs such as type classes and generics that Chisel circuits are parameterized by are very difficult to represent in SystemVerilog. The open-source Chisel Verification Library remedies this disconnect between Chisel and UVM by providing high level verification constructs for Chisel testbenches. It is modeled off of UVM to contain the benefits of the test component abstractions such as the driver and monitor, and it also supports common interfaces such as the Decoupled and TileLink interface. Moreover, the library includes a SVA-like specification language eDSL that enable users to write property assertions on output traces. The library has been used in several applications, such as the verification of a RAM module, L2 cache, as well as an AES cryptography accelerator.},
}

EndNote citation:

%0 Thesis
%A Tsai, Yuan-Cheng 
%T Dynamic Verification Library for Chisel
%I EECS Department, University of California, Berkeley
%D 2021
%8 May 15
%@ UCB/EECS-2021-132
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-132.html
%F Tsai:EECS-2021-132