Adhiraj Datar

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2021-161

June 13, 2021

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-161.pdf

Several NP-hard combinatorial optimization problems such as vehicle routing, optimal graph traversal and automatic ASIC place-and-route have direct practical applications. However, as the demand for highly scaled processing of these problems grows, traditional sequential and synchronous processor-based solutions incur exponential processing penalties and fail to keep up in performance. This project outlines the Parallel Asynchronous Stochastic Sampling Optimizer (PASSO) — a novel neural accelerator based on the Ising model that demonstrates a theoretical 250x power and 3x performance speedup over state-of-the-art systems on a 100-node Max-Cut problem. Specifically, this work highlights the design choices and implementation of the digital configuration, sampling and data streamout systems in the PASSO accelerator. In addition, the report covers the physical design and integration of the chip at the top level which was performed to submit the first PASSO design (PASSOv1) for tapeout in the GlobalFoundries 12LP process in April 2021.

Advisors: Sayeef Salahuddin

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BibTeX citation:

@mastersthesis{Datar:EECS-2021-161,
    Author= {Datar, Adhiraj},
    Title= {Digital System Design and Fullchip Integration for Asynchronous Stochastic Neural Accelerator},
    School= {EECS Department, University of California, Berkeley},
    Year= {2021},
    Month= {Jun},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-161.html},
    Number= {UCB/EECS-2021-161},
    Abstract= {Several NP-hard combinatorial optimization problems such as vehicle routing, optimal graph traversal and automatic ASIC place-and-route have direct practical applications. However, as the demand for highly scaled processing of these problems grows, traditional sequential and synchronous processor-based solutions incur exponential processing penalties and fail to keep up in performance. This project outlines the Parallel Asynchronous Stochastic Sampling Optimizer (PASSO) — a novel neural accelerator based on the Ising model that demonstrates a theoretical 250x power and 3x performance speedup over state-of-the-art systems on a 100-node Max-Cut problem. Specifically, this work highlights the design choices and implementation of the digital configuration, sampling and data streamout systems in the PASSO accelerator. In addition, the report covers the physical design and integration of the chip at the top level which was performed to submit the first PASSO design (PASSOv1) for tapeout in the GlobalFoundries 12LP process in April 2021.},
}

EndNote citation:

%0 Thesis
%A Datar, Adhiraj 
%T Digital System Design and Fullchip Integration for Asynchronous Stochastic Neural Accelerator
%I EECS Department, University of California, Berkeley
%D 2021
%8 June 13
%@ UCB/EECS-2021-161
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-161.html
%F Datar:EECS-2021-161