Zitao Fang

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2022-150

May 19, 2022

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-150.pdf

The end of Moore's Law has motivated numerous innovations in computer architecture. The traditional approach of increasing frequency and numbers of transistors for general-purpose computation hardware are facing diminishing return, and we must turn to data-level parallelism and specialized hardware accelerator for performance growth. This thesis describes a simple RISC-V vector unit implementation based on a microcode expander. We found that even if we are only using one data path, we still get considerable performance improvement on some benchmark tests over scalar code. We also demonstrate that we can reuse existing hardware to implement custom instructions with minimum hardware overhead by mapping a DSL for accelerator generation onto the microcode expander.

Advisors: Krste Asanović

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BibTeX citation:

@mastersthesis{Fang:EECS-2022-150,
    Author= {Fang, Zitao},
    Title= {LEM: A Configurable RISC-V Vector Unit Based on Parameterized Microcode Expander},
    School= {EECS Department, University of California, Berkeley},
    Year= {2022},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-150.html},
    Number= {UCB/EECS-2022-150},
    Abstract= {  The end of Moore's Law has motivated numerous innovations in computer architecture. The traditional approach of increasing frequency and numbers of transistors for general-purpose computation hardware are facing diminishing return, and we must turn to data-level parallelism and specialized hardware accelerator for performance growth. This thesis describes a simple RISC-V vector unit implementation based on a microcode expander. We found that even if we are only using one data path, we still get considerable performance improvement on some benchmark tests over scalar code. We also demonstrate that we can reuse existing hardware to implement custom instructions with minimum hardware overhead by mapping a DSL for accelerator generation onto the microcode expander.},
}

EndNote citation:

%0 Thesis
%A Fang, Zitao 
%T LEM: A Configurable RISC-V Vector Unit Based on Parameterized Microcode Expander
%I EECS Department, University of California, Berkeley
%D 2022
%8 May 19
%@ UCB/EECS-2022-150
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-150.html
%F Fang:EECS-2022-150