Urmita Sikder

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2022-20

May 1, 2022

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-20.pdf

The emergence of the Internet of Things (IoT) has made energy efficiency a key requirement for integrated electronic systems. Nanoelectromechanical (NEM) switches have the ideal characteristics of zero OFF-state leakage and small subthreshold swing, making them promising candidates for ultra-low-power digital computing applications. IoT has also motivated the development of new computing architectures that are more energy-efficient than the classic von Neumann architecture. An “in-memory computing” architecture avoids the need for data communication between separate processing and memory units, and hence achieves more energy-efficient operation. For such a computing architecture, it is desirable to have compact non-volatile (NV) memory cells that can be programmed and read with very low energy.

Utilization of back-end-of-line (BEOL) metallic interconnect layers to implement non-volatile NEM switches is an attractive approach for monolithic integration with CMOS transistors, which can enable enhanced chip functionality with relatively low incremental manufacturing cost. This dissertation addresses the fabrication challenges for realizing BEOL NEM switches and demonstrates their suitability for implementation of new computing architectures. Etch recipes and cleaning techniques are developed and optimized to successfully achieve BEOL NEM switches using standard 65nm and 16nm CMOS manufacturing processes, for the first time.

This dissertation also presents a new, vertically oriented NEM switch design implemented using multiple BEOL layers to achieve a more compact footprint. Design trade-offs are investigated, and design constraints for reliable and energy-efficient operation are discussed. A design optimization framework is presented to minimize the energy-delay product associated with the programming operation of a NEM switch.

Prototype reconfigurable hybrid CMOS-NEM circuits comprising arrays of BEOL NV-NEM switches are experimentally demonstrated for the first time, showing their promise for compact, energy-efficient and fast memory-based data searching and look-up table operation.

Scaling of NV-NEM switches to smaller dimensions is projected to lower their operating voltage, in order to be compatible with standard CMOS transistors, as well as to improve their energy-delay performance. The read/ write energy and read delay of the vertically oriented NV-NEM switch are projected to compare very favorably against the same performance parameters of other emerging embedded NV memory technologies.

Advisors: Tsu-Jae King Liu

---

BibTeX citation:

@phdthesis{Sikder:EECS-2022-20,
    Author= {Sikder, Urmita},
    Title= {Nanoelectromechanical Switch Design and Implementation in Back-End-of-Line Technology},
    School= {EECS Department, University of California, Berkeley},
    Year= {2022},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-20.html},
    Number= {UCB/EECS-2022-20},
    Abstract= {The emergence of the Internet of Things (IoT) has made energy efficiency a key requirement for integrated electronic systems. Nanoelectromechanical (NEM) switches have the ideal characteristics of zero OFF-state leakage and small subthreshold swing, making them promising candidates for ultra-low-power digital computing applications. IoT has also motivated the development of new computing architectures that are more energy-efficient than the classic von Neumann architecture. An “in-memory computing” architecture avoids the need for data communication between separate processing and memory units, and hence achieves more energy-efficient operation. For such a computing architecture, it is desirable to have compact non-volatile (NV) memory cells that can be programmed and read with very low energy.

Utilization of back-end-of-line (BEOL) metallic interconnect layers to implement non-volatile NEM switches is an attractive approach for monolithic integration with CMOS transistors, which can enable enhanced chip functionality with relatively low incremental manufacturing cost. This dissertation addresses the fabrication challenges for realizing BEOL NEM switches and demonstrates their suitability for implementation of new computing architectures. Etch recipes and cleaning techniques are developed and optimized to successfully achieve BEOL NEM switches using standard 65nm and 16nm CMOS manufacturing processes, for the first time.

This dissertation also presents a new, vertically oriented NEM switch design implemented using multiple BEOL layers to achieve a more compact footprint. Design trade-offs are investigated, and design constraints for reliable and energy-efficient operation are discussed. A design optimization framework is presented to minimize the energy-delay product associated with the programming operation of a NEM switch. 

Prototype reconfigurable hybrid CMOS-NEM circuits comprising arrays of BEOL NV-NEM switches are experimentally demonstrated for the first time, showing their promise for compact, energy-efficient and fast memory-based data searching and look-up table operation. 

Scaling of NV-NEM switches to smaller dimensions is projected to lower their operating voltage, in order to be compatible with standard CMOS transistors, as well as to improve their energy-delay performance. The read/ write energy and read delay of the vertically oriented NV-NEM switch are projected to compare very favorably against the same performance parameters of other emerging embedded NV memory technologies.},
}

EndNote citation:

%0 Thesis
%A Sikder, Urmita 
%T Nanoelectromechanical Switch Design and Implementation in Back-End-of-Line Technology
%I EECS Department, University of California, Berkeley
%D 2022
%8 May 1
%@ UCB/EECS-2022-20
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-20.html
%F Sikder:EECS-2022-20