Modeling EOL Degradation for NBTI Reliability of Low EOT Negative Capacitance p-SOI MOSFETs

Neeraj Shenoy

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2023-175
May 12, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-175.pdf

Bias temperature instability (BTI) has become an increasingly pressing degradation mechanism due to its impact on the reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs). BTI results in a gradual shift of MOSFET characteristics, such as threshold voltage (VT), over time. We are interested in the reliability of p-type silicon-on-insulator (SOI) MOSFETs (Lg = 90 nm) incorporating a 1.8 nm HfO2-ZrO2 superlattice (HZH) gate stack. This gate stack exhibits an effective oxide thickness of 7.5 Å due to negative capacitance (NC) effects. In this paper, we estimate the end-of-life (EOL) degradation of threshold voltage (ΔVT) of low EOT NC p-SOI MOSFETs using a negative bias temperature instability (NBTI) physical model. The model is created based on experimental data of stress time (tSTR) and ΔVT of p-SOI MOSFETs under constant temperature (T = 85℃) and varying overdrive voltage (VOV) conditions. We find ΔVIT, the interface trap contribution, is the major contributor to the overall ΔVT, while ΔVHT and ΔVOT, the hole trapping and bulk trap generation contributions, are negligible. So, we extrapolate the ΔVIT physical model out to tSTR = 10 years ≈ 3 * 108 seconds and find estimates for degradation of ΔVT at EOL. We now have a better sense of the reliability of NC p-SOI MOSFETs under constant T and varying VOV conditions.

Advisor: Jeffrey Bokor

BibTeX citation:

@mastersthesis{Shenoy:EECS-2023-175,
    Author = {Shenoy, Neeraj},
    Editor = {Salahuddin, Sayeef},
    Title = {Modeling EOL Degradation for NBTI Reliability of Low EOT Negative Capacitance p-SOI MOSFETs},
    School = {EECS Department, University of California, Berkeley},
    Year = {2023},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-175.html},
    Number = {UCB/EECS-2023-175},
    Abstract = {<p>Bias temperature instability (BTI) has become an increasingly pressing degradation mechanism due to its impact on the reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs).  BTI results in a gradual shift of MOSFET characteristics, such as threshold voltage (V<sub>T</sub>), over time.  We are interested in the reliability of p-type silicon-on-insulator (SOI) MOSFETs (L<sub>g</sub> = 90 nm) incorporating a 1.8 nm HfO<sub>2</sub>-ZrO<sub>2</sub> superlattice (HZH) gate stack.  This gate stack exhibits an effective oxide thickness of 7.5 &#8491 due to negative capacitance (NC) effects.  In this paper, we estimate the end-of-life (EOL) degradation of threshold voltage (&#916V<sub>T</sub>) of low EOT NC p-SOI MOSFETs using a negative bias temperature instability (NBTI) physical model. The model is created based on experimental data of stress time (t<sub>STR</sub>) and &#916V<sub>T</sub> of p-SOI MOSFETs under constant temperature (T = 85&#8451) and varying overdrive voltage (V<sub>OV</sub>) conditions.  We find &#916V<sub>IT</sub>, the interface trap contribution, is the major contributor to the overall &#916V<sub>T</sub>, while &#916V<sub>HT</sub> and &#916V<sub>OT</sub>, the hole trapping and bulk trap generation contributions, are negligible.  So, we extrapolate the &#916V<sub>IT</sub> physical model out to t<sub>STR</sub> = 10 years &#8776 3 * 10<sup>8</sup> seconds and find estimates for degradation of &#916V<sub>T</sub> at EOL.  We now have a better sense of the reliability of NC p-SOI MOSFETs under constant T and varying V<sub>OV</sub> conditions.</p>}
}

EndNote citation:

%0 Thesis
%A Shenoy, Neeraj
%E Salahuddin, Sayeef
%T Modeling EOL Degradation for NBTI Reliability of Low EOT Negative Capacitance p-SOI MOSFETs
%I EECS Department, University of California, Berkeley
%D 2023
%8 May 12
%@ UCB/EECS-2023-175
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-175.html
%F Shenoy:EECS-2023-175