Christopher Yarp

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2023-47

May 1, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-47.pdf

Real-time, high performance, radio signal processing has traditionally been implemented on custom ASICs or FPGAs. While powerful and efficient, these hardware platforms require extensive engineering effort to create and are relatively inflexible post deployment. Software Radio (SR) presents a compelling alternative to ASIC and FPGA solutions by utilizing the consistently expanding compute power available on CPUs. However, extracting the parallelism available in a radio design and effectively mapping it to the different modes of parallelism available on the CPU (SIMD units, superscalar out-of-order cores, MIMD across cores) to obtain the desired performance is challenging, requiring in-depth knowledge of both the signal processing design and CPU microarchitecture.

This project aims to demonstrate the feasibility of high-performance software radio by identifying causes behind gaps in expected performance vs. achieved performance, developing solutions to address platform and design limitations, and improving designer productivity by providing a flow from signal processing dataflow graphs to optimized multithreaded C applications. To achieve these goals, a variety of tools were developed including a custom written dataflow-graph-to-C compiler (Laminar) which contains optimization passes specifically targeting software implementations of streaming DSP. Performance modeling, benchmarking, and telemetry collection are used to assist DSP co-design and provide insight for future CPU designs.

Advisors: John Wawrzynek

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BibTeX citation:

@phdthesis{Yarp:EECS-2023-47,
    Author= {Yarp, Christopher},
    Title= {High Speed Software Radio on General Purpose CPUs},
    School= {EECS Department, University of California, Berkeley},
    Year= {2023},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-47.html},
    Number= {UCB/EECS-2023-47},
    Abstract= {Real-time, high performance, radio signal processing has traditionally been implemented on custom ASICs or FPGAs.  While powerful and efficient, these hardware platforms require extensive engineering effort to create and are relatively inflexible post deployment.  Software Radio (SR) presents a compelling alternative to ASIC and FPGA solutions by utilizing the consistently expanding compute power available on CPUs.  However, extracting the parallelism available in a radio design and effectively mapping it to the different modes of parallelism available on the CPU (SIMD units, superscalar out-of-order cores, MIMD across cores) to obtain the desired performance is challenging, requiring in-depth knowledge of both the signal processing design and CPU microarchitecture.

This project aims to demonstrate the feasibility of high-performance software radio by identifying causes behind gaps in expected performance vs. achieved performance, developing solutions to address platform and design limitations, and improving designer productivity by providing a flow from signal processing dataflow graphs to optimized multithreaded C applications.  To achieve these goals, a variety of tools were developed including a custom written dataflow-graph-to-C compiler (Laminar) which contains optimization passes specifically targeting software implementations of streaming DSP.  Performance modeling, benchmarking, and telemetry collection are used to assist DSP co-design and provide insight for future CPU designs.},
}

EndNote citation:

%0 Thesis
%A Yarp, Christopher 
%T High Speed Software Radio on General Purpose CPUs
%I EECS Department, University of California, Berkeley
%D 2023
%8 May 1
%@ UCB/EECS-2023-47
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-47.html
%F Yarp:EECS-2023-47