Improving LLM Performance in Generating Verilog by Fine Tuning with a Translated Code Dataset

Brendan Roberts

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2025-104
May 16, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-104.pdf

Advisor: Sophia Shao

\"Edit"; ?>

BibTeX citation:

@mastersthesis{Roberts:EECS-2025-104,
    Author = {Roberts, Brendan},
    Title = {Improving LLM Performance in Generating Verilog by Fine Tuning with a Translated Code Dataset},
    School = {EECS Department, University of California, Berkeley},
    Year = {2025},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-104.html},
    Number = {UCB/EECS-2025-104}
}

EndNote citation:

%0 Thesis
%A Roberts, Brendan
%T Improving LLM Performance in Generating Verilog by Fine Tuning with a Translated Code Dataset
%I EECS Department, University of California, Berkeley
%D 2025
%8 May 16
%@ UCB/EECS-2025-104
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-104.html
%F Roberts:EECS-2025-104