Zhaokai Liu

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2025-21

May 1, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-21.pdf

High-speed analog-to-digital converters (ADCs) are critical components in wideband wireline and wireless communication systems. Rapid advancements in communication systems require medium-to-high resolution ADCs that can digitize a wide spectrum with high power efficiency. In addition to the strict performance demands, the design of ADC, as analog and mixed-signal circuits becomes progressively more complex and time-consuming at advanced technology nodes. The design challenges arise not only from the scaled supply voltage and increased variation, but also from the more complex layout, the explosion of design rules, and increased vulnerability to parasitic effects. To address these challenges, this dissertation presents an automated and process-portable ADC generator framework capable of creating instances that support a sampling rate of up to 4GS/s and achieve an ENOB higher than 9 bits. The generator is developed using Berkeley Analog Generator (BAG), which enables automated circuit generation, speeds up the design iteration, and significantly improves design reusability.

Traditional voltage and time domain data conversion are explored to explore circuit-level techniques suitable for scaled processes with high programmability and reusability. The proposed generator incorporates the successive approximation register (SAR) architecture, which has become prevalent in the field due to its ability to eliminate the need for precision analog components. Furthermore, the utilization of time-based data conversion techniques, such as ring oscillator-based voltage-controlled oscillator (VCO) data conversion and ring amplifiers, has shown promising results in terms of design metrics for implementing precise analog functions in scaled technologies. In the proposed generator, the VCO-based ADC is used for second-stage fine conversion, while the ring amplifier is used for residue amplification. A process-portable automated ADC generator, which supports a wide range of specifications, is developed by integrating and selectively enabling these techniques. The standalone SAR ADC generator has been ported to various processes and utilized to create designs with diverse specifications, showcasing the effectiveness of the generator-based methodology. The complete circuit architecture of the proposed ADC generator, which achieves maximum performance, is based on a time-interleaved (TI) subranging ADC array. The sub-ADC uses a pipelined topology that combines both the SAR and the VCO-based ADCs to enhance the resolution. The ADC generator is fully automated and parameterized, generating designs that are compliant with design rules based on input parameters.

Finally, this thesis exemplifies the effectiveness of the generator-based design methodology through the creation of multiple generated prototypes of time-interleaved ADC designs using both BAG2 and BAG3 frameworks. As the main focus of this thesis, two prototypes were generated using the proposed generator to implement TI SAR-VCO ADCs with 4 and 8 channels, respectively. The 4-way interleaved design implemented in the Intel 22FFL process samples the input at a rate of 2GS/s. And the 8-way time-interleaved prototype samples at 4GS/s and is implemented using the Intel 16 process. The measurement setup and results of the latest prototype chip are presented to demonstrate the performance of the proposed ADC generator. The ADC achieves a peak SFDR of 72dB and a resolution of over 9 bits within the 2GHz Nyquist band. The total power consumption of the prototype under a 0.9V supply is 124.6mW. The prototype achieves a Schreier figure-of-merit (FOM) of 158.4dB and a Walden figure-of-merit of 60.5fJ/conv.-step. In summary, this thesis presents both circuit techniques and analog design automation. The proposed generator demonstrates promising ways of implementing automated and process-portable ADC designs with high reconfigurability using a generator-based methodology.

Advisors: Borivoje Nikolic

---

BibTeX citation:

@phdthesis{Liu:EECS-2025-21,
    Author= {Liu, Zhaokai},
    Title= {Automated and Process-Portable Generation of Data Converters},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-21.html},
    Number= {UCB/EECS-2025-21},
    Abstract= {High-speed analog-to-digital converters (ADCs) are critical components in wideband wireline and wireless communication systems. Rapid advancements in communication systems require medium-to-high resolution ADCs that can digitize a wide spectrum with high power efficiency. In addition to the strict performance demands, the design of ADC, as analog and mixed-signal circuits becomes progressively more complex and time-consuming at advanced technology nodes. The design challenges arise not only from the scaled supply voltage and increased variation, but also from the more complex layout, the explosion of design rules, and increased vulnerability to parasitic effects. To address these challenges, this dissertation presents an automated and process-portable ADC generator framework capable of creating instances that support a sampling rate of up to 4GS/s and achieve an ENOB higher than 9 bits. The generator is developed using Berkeley Analog Generator (BAG), which enables automated circuit generation, speeds up the design iteration, and significantly improves design reusability.

Traditional voltage and time domain data conversion are explored to explore circuit-level techniques suitable for scaled processes with high programmability and reusability.
The proposed generator incorporates the successive approximation register (SAR) architecture, which has become prevalent in the field due to its ability to eliminate the need for precision analog components. Furthermore, the utilization of time-based data conversion techniques, such as ring oscillator-based voltage-controlled oscillator (VCO) data conversion and ring amplifiers, has shown promising results in terms of design metrics for implementing precise analog functions in scaled technologies.
In the proposed generator, the VCO-based ADC is used for second-stage fine conversion, while the ring amplifier is used for residue amplification.
A process-portable automated ADC generator, which supports a wide range of specifications, is developed by integrating and selectively enabling these techniques. The standalone SAR ADC generator has been ported to various processes and utilized to create designs with diverse specifications, showcasing the effectiveness of the generator-based methodology.
The complete circuit architecture of the proposed ADC generator, which achieves maximum performance, is based on a time-interleaved (TI) subranging ADC array. The sub-ADC uses a pipelined topology that combines both the SAR and the VCO-based ADCs to enhance the resolution.
The ADC generator is fully automated and parameterized, generating designs that are compliant with design rules based on input parameters.

Finally, this thesis exemplifies the effectiveness of the generator-based design methodology through the creation of multiple generated prototypes of time-interleaved ADC designs using both BAG2 and BAG3 frameworks. As the main focus of this thesis, two prototypes were generated using the proposed generator to implement TI SAR-VCO ADCs with 4 and 8 channels, respectively. The 4-way interleaved design implemented in the Intel 22FFL process samples the input at a rate of 2GS/s.
And the 8-way time-interleaved prototype samples at 4GS/s and is implemented using the Intel 16 process. The measurement setup and results of the latest prototype chip are presented to demonstrate the performance of the proposed ADC generator. The ADC achieves a peak SFDR of 72dB and a resolution of over 9 bits within the 2GHz Nyquist band. The total power consumption of the prototype under a 0.9V supply is 124.6mW. The prototype achieves a Schreier figure-of-merit (FOM) of 158.4dB and a Walden figure-of-merit of 60.5fJ/conv.-step. In summary, this thesis presents both circuit techniques and analog design automation. The proposed generator demonstrates promising ways of implementing automated and process-portable ADC designs with high reconfigurability using a generator-based methodology.},
}

EndNote citation:

%0 Thesis
%A Liu, Zhaokai 
%T Automated and Process-Portable Generation of Data Converters
%I EECS Department, University of California, Berkeley
%D 2025
%8 May 1
%@ UCB/EECS-2025-21
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-21.html
%F Liu:EECS-2025-21