Delay-Locked Loops for Multiphase Clock Generation

Oliver Yu

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2025-86
May 16, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-86.pdf

The trend towards chiplet-based architectures not only places strict requirements on high-speed die-to-die interconnects, as defined within the Universal Chiplet Interconnect Express (UCIe) standard, but also creates opportunities to innovate on the designs of these interconnects. Clocking circuits such as delay-locked loops (DLLs) play a crucial role in these high-bandwidth communication links by generating evenly spaced clock phases to support serialization and timing alignment between high-speed signals. As per-lane data rates reach 16 GT/s and higher, clock precision and phase linearity requirements become more stringent. This work is motivated by these demands and explores the design of a digitally controlled DLL architecture targeting the performance needs of UCIe-based die-to-die links.

A digitally-controlled multiphase DLL operating at 8GHz, implemented in the Intel 16 CMOS process, is presented. The DLL achieves 37.96fs RMS jitter and 1.16ps of deterministic jitter while occupying a total area of 32.4µm by 54.63µm and consuming 12.5mW of power. The integrated clock lane targets a full 360 degree phase coverage, achieving a 15.6mUI phase resolution with a DNL of 0.2825 LSBs and an INL of 2.245 LSBs. The design was taped out as part of the UCIe module on the Kodiak chip, aiming to contribute to scalable clocking solutions for multi-die systems. This work highlights design challenges and considerations in developing delay locked loops for clocking architectures that meet the precision demands of modern chiplet ecosystems.

Advisor: Borivoje Nikolic

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BibTeX citation:

@mastersthesis{Yu:EECS-2025-86,
    Author = {Yu, Oliver},
    Title = {Delay-Locked Loops for Multiphase Clock Generation},
    School = {EECS Department, University of California, Berkeley},
    Year = {2025},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-86.html},
    Number = {UCB/EECS-2025-86},
    Abstract = {The trend towards chiplet-based architectures not only places strict requirements on high-speed die-to-die interconnects, as defined within the Universal Chiplet Interconnect Express (UCIe) standard, but also creates opportunities to innovate on the designs of these interconnects. Clocking circuits such as delay-locked loops (DLLs) play a crucial role in these high-bandwidth communication links by generating evenly spaced clock phases to support serialization and timing alignment between high-speed signals. As per-lane data rates reach 16 GT/s and higher, clock precision and phase linearity requirements become more stringent. This work is motivated by these demands and explores the design of a digitally controlled DLL architecture targeting the performance needs of UCIe-based die-to-die links. 

A digitally-controlled multiphase DLL operating at 8GHz, implemented in the Intel 16 CMOS process, is presented. The DLL achieves 37.96fs RMS jitter and 1.16ps of deterministic jitter while occupying a total area of 32.4µm by 54.63µm and consuming 12.5mW of power. The integrated clock lane targets a full 360 degree phase coverage, achieving a 15.6mUI phase resolution with a DNL of 0.2825 LSBs and an INL of 2.245 LSBs. The design was taped out as part of the UCIe module on the Kodiak chip, aiming to contribute to scalable clocking solutions for multi-die systems. This work highlights design challenges and considerations in developing delay locked loops for clocking architectures that meet the precision demands of modern chiplet ecosystems.}
}

EndNote citation:

%0 Thesis
%A Yu, Oliver
%T Delay-Locked Loops for Multiphase Clock Generation
%I EECS Department, University of California, Berkeley
%D 2025
%8 May 16
%@ UCB/EECS-2025-86
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-86.html
%F Yu:EECS-2025-86