An Assume-Guaranteee Rule for Checking Simulation for Multipoint Moment Matching of Multiport Distributed Interconnect Networks (M99/13)
Thomas A. Henzinger, S. Qadeer, S.K. Rajamani, S. Tasiran, J.M.L. Wang and Ernest S. Kuh

Passive Model Order Reduction Algorithm for Multipoint Moment Matching of Multiport Distributed Interconnect Networks (M98/13)
Q. Yu, J.M.L. Wang and Ernest S. Kuh

Reduced Order Model of Transmission Lines by Multiple Points Moment Matching and Passivity Preservation (M97/70)
Q. Yu and Ernest S. Kuh

Post Global Routing Crosstalk Risk Estimation and Reduction (M96/13)
T. Xue, Ernest S. Kuh and D. Wang

An Interactive Floorplanner for Design Space Exploration (M96/4)
H. Esbensen and Ernest S. Kuh

Design Space Exploration for Building- Block Placements (M95/84)
H. Esbensen and Ernest S. Kuh

SYMPHONY: An Efficient Mixed Signal Circuit Simulator (M95/24)
P. Buch and Ernest S. Kuh

An IC/MCM Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration (M95/20)
H. Esbensen and Ernest S. Kuh

An Accurate Time Domain Interconnect Model of Transmission Line Networks (M95/10)
Q. Yu and Ernest S. Kuh

Techniques for Fast Circuit Simulation Applied to Power Estimation of CMOS Circuits (M94/98)
P. Buch, S. Lin, V. Nagasamy and Ernest S. Kuh

New Approaches for On-Chip Power Switching Noise Reduction (M94/94)
C. Hough, T. Xue and Ernest S. Kuh

Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation (M94/20)
Q. Yu and Ernest S. Kuh

Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device (M93/42)
N.B. Bhat, K. Chaudhary and Ernest S. Kuh

Quadratic Boolean Programming for Performance-Driven System Partitioning (M93/19)
M. Shih and Ernest S. Kuh

Integer Programming Techniques for Multiway System Partitioning Undertiming and Capacity Constraints (M92/81)
M. Shih, Ernest S. Kuh and R-S. Tsay

RITUAL: A Performance Driven Placement Algorithm (M91/103)
A. Srinivasan, K. Chaudhary and Ernest S. Kuh

RITUAL An Algorithm for Performance-Driven Placement of Cell-Based ICs (M91/47)
A. Srinivasan, K. Chaudhary and Ernest S. Kuh

Novel Routing Schemes for IC Layout Part II: Three-Layer Channel Routing (M90/102)
D. Wang and Ernest S. Kuh

Novel Routing Schemes for IC Layout Part I: Two-Layer Channel Routing (M90/101)
D. Wang and Ernest S. Kuh

A Novel Approach to IC Performance Optimization by Clock Routing (M90/27)
M.A.B. Jackson, A. Srinivasan and Ernest S. Kuh

A Unified Approach to the Via Minimization Problem (M87/80)
X-M. Xiong and Ernest S. Kuh

PROUD: A Fast Sea-of-Gates Placement Algorithm (M87/79)
R-S. Tsay, Ernest S. Kuh and C-P. Hsu

A Unified Approach to Circuit Partitioning and Placement (M86/8)
R-S. Tsay and Ernest S. Kuh

Building Block Layout: Routing Region Definition and Ordering Scheme (M85/14)
W.M. Dai, T. Asano and Ernest S. Kuh

BBL.2 User's Manual (M85/2)
N.-P. Chen, C.-C. Chen, C.-P. Hsu, H.H. Chen, Ernest S. Kuh and M. Marek-Sadowska

RAMP: Gate-Array, Standard-Cell and Masterimage Placement Manual (M84/71)
C.K. Cheng and Ernest S. Kuh

BBL User's Manual (M83/68)
N-P. Chen, C-P. Hsu, H.H. Chen, Ernest S. Kuh and M. Marek-Sadowska

Module Placement Based on Resistive Network Optimization (M83/35)
C.K. Cheng and Ernest S. Kuh

An Efficient Single-Row Routing Algorithm (M83/34)
T. T-S. Tarng, M. Marek-Sadowska and Ernest S. Kuh

Berkeley Building-Block Layout System for VLSI Design (M83/10)
N.P. Chen, C.P. Hsu and Ernest S. Kuh