Ph.D. Dissertations - Robert K. Brayton

Efficient Abstraction and Refinement for Word-level Model Checking
Yen-Sheng Ho [2017]

Reasoning about High-Level Constructs in Hardware/Software Formal Verification
Jiang Long [2017]

Verification and Synthesis of Clock-Gated Circuits
Yu-Yun Dai [2017]

Scalable Model Checking Beyond Safety - A Communication Fabric Perspective
Sayak Ray [2013]

On Invariants to Characterize the State Space for Sequential Logic Synthesis and Formal Verification
Mike Case [2009]

Clock Driven Design Planning
Shauki Elassaad [2008]

Sequential Optimization for Low Power Digital Design
Aaron P. Hurst [2008]

On Algorithms for Technology Mapping
Satrajit Chatterjee [2007]

Integration of Physical Design and Sequential Optimization
Philip Chong [2006]

Synthesis Methodology for Built-In At-Speed Testing
Yinghua Li [2005]

Discovering Invariants in the Analysis and Verification of Finite State Transition Systems
Jie-Hong Roland Jiang [2004]

Design Flow for Deep Sub-Micron Integrated Circuits
Fan Mo [2003]

On Efficient Software Realization of Sequential Machines
Yunjian Jiang [2003]

SPFDs: A New Approach to Flexibility in Logic Synthesis
Subarnarekha Sinha [2002]

Propositional Satisfiability Algorithms in EDA Applications
Mukul Ranjan Prasad [2001]

Formal Verification Using Datapath Abstraction
Adrian J. Isles [2000]

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
Sunil P. Khatri [1999]

Compilation, Synthesis, and Simulation of Hardware Description Languages: The Compositional Models of HDL's
Szu-Tsung Cheng [1998]

Compositional and Hierarchical Techniques for the Formal Verification of Real-Time Systems
Serdar Tasiran [1998]

Omega-Automata, Games, and Synthesis
Sriram C. Krishnan [1998]

Timing Analysis and Optimization for High-Performance Digital Circuits
Yuji Kukimoto [1998]

Design and Implementation Verification of Finite State Systems
Rajeev K. Ranjan [1997]

A BDD-Based Environment for Formal Verification of Hardware Systems
Ramin Hojati [1996]

Design Replacements for Sequential Circuits
Vigyan Singhal [1996]

Formal Methods in VLSI System Design
Adnan Aziz [1996]

Hierarchical Sequential Synthesis: Logic Synthesis of FSM Networks
Huey-yih Wang [1996]

Incremental Methods for Formal Verification and Logic Synthesis
Gitanjali M. Swamy [1996]

State Minimization of Finite State Machines Using Implicit Techniques
Timothy Y.-K. Kam [1995]

Logic Optimization of Interacting Components in Synchronous Digital Systems
Yosinori Watanabe [1994]

Logical Mapping of Analog Waveforms in Digital Sequential Circuits
Paul R. Stephan [1994]

Algrebraic Methods for Timing Analysis and Testing in High-Performance Designs
William K.-C. Lam [1993]

Sequential Circuit Synthesis at the Gate Level
Ellen M. Sentovich [1993]

Don't Cares in Multi-Level Network Optimization
Hamid Savoj [1992]

Partitioning and Scheduling for Circuit Simulation
Antony P.-C. Ng [1992]

Synthesis and Verification of Asynchronous Circuits from Graphical Specifications
Cho W. Moon [1992]

The High-Level Synthesis of Microprocessors Using Instruction Frequency Statistics
William R. Bush [1992]

Performance and Testability Interactions in Logic Synthesis
Alexander Saldanha [1991]

Combinational Logic Optimization Techniques in Sequential Logic Analysis
Sharad Malik [1990]

Performance-Oriented Technology Mapping
Herve J. Touati [1990]

On the Interaction of Functional and Timing Behaviour of Combinational Logic Circuits
Patrick C. McGeer [1989]

An Interactive Information Organization and Retrieval System in a Time-Sharing Environment
Mehdi B. Kermani [1969]