Borivoje Nikolic
Teaching Schedule
Fall 2024
- EE 194. Test Integrated Circuit Chips Designed in Previous Tapeout Classes, TuTh 11:00-11:59, Off Campus
- EE 290-6. Test Integrated Circuit Chips Designed in Previous Tapeout Classes, TuTh 11:00-11:59, Off Campus
Spring 2025
- EECS 251B. Advanced Digital Integrated Circuits and Systems, Fr 13:00-15:59, Cory 540AB
Biography
He lectured electronics courses at the University of Belgrade from 1992 to 1996. He spent two years with Silicon Systems, Inc., Texas Instruments Storage Products Group, San Jose, CA, working on disk-drive signal processing electronics. In 1999, he joined the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, where he is now a Professor. His research activities include digital and analog integrated circuit design and VLSI implementation of communications and signal processing algorithms. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003.
Dr. Nikolić received the NSF CAREER award in 2003, College of Engineering Best Doctoral Dissertation Prize and Anil K. Jain Prize for the Best Doctoral Dissertation in Electrical and Computer Engineering at University of California at Davis in 1999, as well as the City of Belgrade Award for the Best Diploma Thesis in 1992. For work with his students and colleagues he has received the best paper awards at the IEEE International Solid-State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Device Research Conference, and the ACM/IEEE International Symposium of Low-Power Electronics.
Education
- 1999, Ph.D., Electrical and Computer Engineering, UC Davis
- 1994, M.Sc., Electrical Engineering, University of Belgrade, Serbia
- 1992, Dipl.Ing., Electrical Engineering, University of Belgrade, Serbia
Selected Publications
- J. Kwak and B. Nikolic, "A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI," IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2368-2379, Oct. 2016.
- X. Xiao, A. Pratt, A. Niknejad, E. Alon, and B. Nikolic, "A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use," in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 181-184.
- B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolic, "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC," in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 269-272.
- A. Whitcombe, S. Taylor, M. Denham, V. Milovanović, and B. Nikolic, "On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS," in 2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, pp. 248-251.
- S. Ramakrishnan, L. Calderin, A. Puglielli, E. Alon, A. Niknejad, and B. Nikolic, "A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage," in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1-2.
- M. Blagojević, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, and B. Nikolic, "A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI," in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1-2.
- B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtić, B. Keller, S. Bailey, M. Blagojević, P. F. Chiu, H. P. Le, P. H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, and B. Nikolic, "A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC #x2013;DC Converters in 28 nm FDSOI," IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 930-942, April 2016.
- D. Stepanovic and B. Nikolic, "A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 48, no. 4, pp. 971-982, April 2013.
- S. O. Toh, Z. Guo, T. King Liu, and B. Nikolic, "Characterization of Dynamic SRAM Stability in 45 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 46, no. 11, pp. 2702-2712, Nov. 2011.
- Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors," Solid-State Circuits, IEEE Journal of, vol. 45, no. 4, pp. 843-855, April 2010.
- Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-Scale SRAM Variability Characterization in 45 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 44, no. 11, pp. 3174-3192, Nov. 2009.
- Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004.
- D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
- J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Pearson Education, 2003.
Awards, Memberships and Fellowships
- SSCS Innovative Education Award, 2024
- Institute of Electrical & Electronics Engineers (IEEE) Fellow, 2017
- IEEE Electron Devices Society (EDS) Fellows, 2017
