Faculty Publications - Krste Asanović

Book chapters or sections

  • K. Asanović, "Vector Processing," in Digital Systems and Applications, V. G. Oklobdzija, Ed., 2nd ed., The Computer Engineering Handbook, Boca Raton, FL: CRC Press, 2007, pp. 1-25-1-35.
  • K. Asanović, J. L. Hennessy, and D. A. Patterson, "Appendix F: Vector Processors," in Computer Architecture: A Quantitative Approach, 4 ed., Boston, MA: Morgan Kaufmann Publishers, 2006.
  • K. Asanović, J. Beck, D. Johnson, B. Kingsbury, N. Morgan, and J. Wawrzynek, "Training Neural Networks with SPERT-II," in Parallel Architectures for Artificial Networks - Paradigms and Implementations, N. Sundararajan, Ed., Los Alamitos, CA: IEEE Computer Society Press, 1998, pp. 345-364.
  • K. Asanović, B. Kingsbury, and N. Morgan, "A Highly Pipelined Architecture for Neural Network Training," in Silicon Architectures for Neural Nets, M. Sami and J. Calzadilla-Daguerre, Eds., Elsevier Press, 1991, pp. 217-232.

Articles in journals or magazines

Articles in conference proceedings

  • S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra, Q. Huang, K. Kovacs, B. Nikolic, R. H. Katz, J. Bachrach, and K. Asanović, "FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud," in Proceedings of the 45th Annual International Symposium on Computer Architecture, ISCA '18, Piscataway, NJ, USA: IEEE Press, 2018, pp. 29--42.
  • B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolic, "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC," in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 269-272.
  • D. Kim, A. Izraelevitz, C. Celio, H. Kim, B. Zimmer, Y. Lee, J. Bachrach, and K. Asanović, "Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL," in ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016, pp. 128-139. [abstract]
  • M. Maas, E. Love, E. Stefanov, M. Tiwari, E. Shi, K. Asanović, J. D. Kubiatowicz, and D. Song, "Phantom: Practical oblivious computation in a secure processor," in Proceedings of the 2013 ACM SIGSAC conference on Computer \& communications security, 2013, pp. 311--324.
  • H. Cook, M. Moreto, S. Bird, K. Dao, D. A. Patterson, and K. Asanović, "A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness," in Proceedings of the 40th Annual International Symposium on Computer Architecture, ACM, 2013, pp. 308-319. [abstract]
  • M. Maas, P. Reames, J. Morlan, K. Asanović, A. D. Joseph, and J. D. Kubiatowicz, "GPUs as an Opportunity for Offloading Garbage Collection," in Proceedings of the 2012 International Symposium on Memory Management, ISMM '12, New York, NY, USA: ACM, 2012, pp. 25--36.
  • S. Beamer, K. Asanović, and D. A. Patterson, "Direction-optimizing breadth-first search," in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, IEEE Computer Society, 2012. [abstract]
  • M. Tiwari, P. Mohan, A. Osheroff, H. Alkaff, E. Love, E. Shi, D. Song, and K. Asanović, "Context-centric Security," in Proceedings of the 7th USENIX Workshop on Hot Topics in Security, HotSec'12, Usenix, 2012.
  • Z. Tan, K. Asanović, and D. A. Patterson, "Datacenter-Scale Network Research on FPGAs," in Proceedings from Workshop on Exascale Evaluation and Research Techniques, 2011. [abstract]
  • Z. Tan, A. Waterman, H. Cook, S. Bird, K. Asanović, and D. A. Patterson, "A Case for FAME: FPGA Architecture Model Execution," in Proceedings of the 37th annual international symposium on Computer architecture, SCA '10, New York, NY: ACM, 2010, pp. 290-301. [abstract]
  • Z. Tan, A. Waterman, R. Avizienis, Y. Lee, H. Cook, D. A. Patterson, and K. Asanović, "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors," in DAC '10 Proceedings of the 47th Design Automation Conference, ACM, 2010, pp. 463-468. [abstract]
  • Z. Tan, K. Asanović, and D. A. Patterson, "An FPGA-based Simulator for Datacenter Networks," in Proccedings of Exascale Evaluation and Research Techniques Workshop, 2010. [abstract]
  • B. C. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting productivity and performance with selective embedded JIT specialization," in Proceedings First Workshop on Programming Models for Emerging Architectures, 2009.
  • S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanovic, "Designing Multi-socket Systems Using Silicon Photonics," in Proceedings 23rd International Conference on Supercomputing, 2009.
  • V. Stojanovic, A. Joshi, C. Batten, Y. Kwon, and K. Asanović, "Manycore processor networks with monolithic integrated CMOS," in 29th Conference on Lasers and Electro-Optics (CLEO'09), 2009.
  • A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanovic, "Silicon-photonic clos networks for global on-chip communication," in NOCS '09: Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, Washington, DC, USA: IEEE Computer Society, 2009, pp. 124--133.
  • A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamin, K. Asanović, and V. Stojanovic, "Silicon-Photonic Clos Networks for Global On-Chip Communication," in 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009.
  • C. Jones, R. Liu, L. Meyerovich, K. Asanović, and R. Bodik, "Parallelizing the Web Browser," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
  • R. Liu, K. Klues, S. Bird, S. Hofmeyr, K. Asanović, and J. D. Kubiatowicz, "Tessellation: Space-Time Partitioning in a Manycore Client OS," in First USENIX Workshop on Hot Topics in ParallelismH, 2009.
  • H. Pan, B. Hindman, and K. Asanović, "Lithe: Enabling Efficient Composition of Parallel Libraries," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
  • C. Batten, H. Aoki, and K. Asanović, "The case for malleable stream architectures," in Workshop on Streaming Systems, 2008.
  • C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanović, "Building manycore processor-to-DRAM networks with monolithic silicon photonics," in Proc. 16th Annual IEEE Symp. on High-Performance Interconnects (HotI 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 21-30.
  • Z. Tan, K. Asanović, and D. A. Patterson, "An FPGA host-multithreaded functional model for SPARC v8," in Proc. 3rd Workshop on Architectural Research Prototyping (WARP-2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 5 pg.
  • J. W. Lee, M. C. Ng, and K. Asanović, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. 35th Intl. Symp. on Computer Architecture (ISCA 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 89-100.
  • M. Hampton and K. Asanović, "Compiling for vector-thread architectures," in Proc. 6th Annual IEEE/ACM Intl. Symp. on Code Generation and Optimization (CGO-2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 205-215.
  • K. Asanović, "Transactors for parallel hardware and software co-design (Invited Paper)," in Proc. 2007 IEEE Intl. High Level Design Validation and Test Workshop (HLDVT-2007), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 140-142.
  • J. W. Lee, M. King, and K. Asanović, "Continual hashing for efficient fine-grain state inconsistency detection," in Proc. 25th IEEE Intl. Conf. on Computer Design (ICCD 2007), Piscataway, NJ: IEEE Press, 2007, pp. 33-40.
  • R. Krashinsky, C. Batten, and K. Asanović, "The Scale Vector-Thread Processor (Winner, DAC/ISSCC Student Design Contest)," in Proc. 44th ACM/IEEE Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 3 pp..
  • S. Crago, J. McMahon, C. Archer, K. Asanović, R. Chaung, K. Goolsbey, M. Hall, C. Kozyrakis, K. Olukotun, U. O'Reilly, R. Pancoast, V. Prasanna, R. Rabbah, S. Ward, and D. Yeung, "CEARCH: Cognition Enabled Architecture," in Proc. 10th Annual Workshop on High Performance Embedded Computing (HPEC 2006), Lexington, MA: MIT Lincoln Laboratory, 2006, pp. 2 pg.
  • V. Paxson, K. Asanović, S. Dharmapurikar, J. W. Lockwood, R. Pang, R. Sommer, and N. Weaver, "Rethinking hardware support for network analysis and intrusion prevention," in Proc. 1st USENIX Workshop on Hot Topics in Security (HotSec '06), Berkeley, CA: USENIX Association, 2006, pp. 63-68.
  • M. Hampton and K. Asanović, "Implementing virtual memory in a vector processor with software restart markers," in Proc. 20th Annual Intl. Conf. on Supercomputing (ICS 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 135-144.
  • J. W. Lee and K. Asanović, "METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors," in Proc. 12th IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS 2006), S. Goddard and J. Liu, Eds., Los Alamitos, CA: IEEE Computer Society Press, 2006, pp. 135-147.
  • R. F. Liu and K. Asanović, "Accelerating architectural exploration using canonical instruction segments," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software (IPASS '06), Piscataway, NJ: IEEE Press, 2006, pp. 13-24.
  • K. C. Barr and K. Asanović, "Branch trace compression for snapshot-based simulation," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS '06), Piscataway, NJ: IEEE Press, 2006, pp. 25-35.
  • G. Gibeling, A. Schultz, and K. Asanović, "The RAMP architecture & description language," in Proc. 2nd Workshop on Architecture Research Using FPGA Platforms (WARFP 2006), 2006, pp. 4 pp..
  • S. Heo and K. Asanović, "Replacing global wires with an on-chip network: A power analysis," in Proc. 2005 Intl. Symp. on Low Power Electronics and Design (ISLPED '05), New York, NY: The Association for Computing Machinery, Inc., 2005, pp. 369-374.
  • M. Zhang and K. Asanović, "Victim replication: Maximizing capacity while hiding wire delay in tiled CMPs," in Proc. 32nd Intl. Symp. on Computer Architecture (ISCA-32), Los Alamitos, CA: IEEE Computer Society, 2005, pp. 336-345.
  • K. C. Barr, H. Pan, M. Zhang, and K. Asanović, "Accelerating multiprocessor simulation with a memory timestamp record," in Proc. IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS 2005), Piscataway, NJ: IEEE Computer Society, 2005, pp. 66-77.
  • D. A. Patterson, K. Asanović, A. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft, and K. A. Yelick, "Intelligent RAM (IRAM): The Industrial Setting, Applications, and Architectures," in Proceedings of ICCD ‘97 International Conference on Computer Design: VLSI in Computers and Processors, ICCD, IEEE, 1997, pp. 2 - 7. [abstract]
  • J. Wawrzynek, K. Asanović, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan, "SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training," in Proceeding of NIPS 8, 1996, pp. 619-625.
  • K. Asanović, J. Beck, B. Irissou, B. Kingsbury, N. Morgan, and J. Wawrzynek, "The T0 Vector Microprocessor," in Proceedings of Hot Chips VII, 1995.
  • K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "A supercomputer for neural computation," in Proc. 1994 IEEE Intl. Conf. on Neural Networks (ICNN '94), Vol. 1, Piscataway, NJ: IEEE Press, 1994, pp. 5-9.
  • K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "Development of a Connectionist Network Supercomputer," in Proceedings of Micro-Neuro 1993, 1993, pp. 253-262.
  • J. Wawrzynek, K. Asanović, and N. Morgan, "The Design of a Neuro-Microprocessor," in Proceedings of IEEE Transactions on Neural Networks, Vol. 4, 1993, pp. 394-399.
  • K. Asanović, J. Beck, B. Kingsubry, P. Kohn, N. Morgan, and J. Wawrzynek, "SPERT: A VLIW/SIMD Neuro-Microprocessor," in Proceedings of IJCNN '92, 1992, pp. II-577-582.
  • K. Asanović, K. Schauser, D. A. Patterson, and E. Frank, "Evaluation of a Stall Cache: An Efficient Restricted On-chip Instruction Cache," in Proceedings of the Hawaii International Conference on System Sciences, HICSS, Vol. 1, 1992, pp. 405-415. [abstract]

Technical Reports

Patents

Ph.D. Theses

Masters Reports