Book chapters or sections

• K. Asanović, "Vector Processing," in Digital Systems and Applications, V. G. Oklobdzija, Ed., 2nd ed., The Computer Engineering Handbook, Boca Raton, FL: CRC Press, 2007, pp. 1-25-1-35.
• K. Asanović, J. L. Hennessy, and D. A. Patterson, "Appendix F: Vector Processors," in Computer Architecture: A Quantitative Approach, 4 ed., Boston, MA: Morgan Kaufmann Publishers, 2006.
• K. Asanović, J. Beck, D. Johnson, B. Kingsbury, N. Morgan, and J. Wawrzynek, "Training Neural Networks with SPERT-II," in Parallel Architectures for Artificial Networks - Paradigms and Implementations, N. Sundararajan, Ed., Los Alamitos, CA: IEEE Computer Society Press, 1998, pp. 345-364.
• K. Asanović, B. Kingsbury, and N. Morgan, "A Highly Pipelined Architecture for Neural Network Training," in Silicon Architectures for Neural Nets, M. Sami and J. Calzadilla-Daguerre, Eds., Elsevier Press, 1991, pp. 217-232.

Articles in journals or magazines

• S. Kim, J. Zhao, K. Asanović, B. Nikolic, and S. Shao, "AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration," IEEE Micro, vol. 44, no. 4, pp. 97-105, July 2024.
• B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtić, B. Keller, S. Bailey, M. Blagojević, P. F. Chiu, H. P. Le, P. H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, and B. Nikolic, "A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC #x2013;DC Converters in 28 nm FDSOI," IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 930-942, April 2016.
• J. Shalf, K. Asanović, D. A. Patterson, K. Keutzer, T. Mattson, and K. A. Yelick, "The Manycore Revolution: Will the HPC Community Lead or Follow?," SciDAC Review, pp. 40-49, 2009.
• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, N. Morgan, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "A View of the Parallel Computing Landscape," Communications of the ACM, vol. 52, no. 10, pp. 56-67, Oct. 2009.
• C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics," IEEE Micro, vol. 29, July 2009.
• A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanovic, "Silicon-Photonic Clos Networks for Global On-Chip Communication," International Symposium of Networks on Chips, vol. 3, Jan. 2009.
• A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanovic, "Silicon-Photonic Clos Networks for Global On-Chip Communication," International Symposium of Networks on Chips, vol. 3, Jan. 2009.
• R. Krashinsky, C. Batten, and K. Asanović, "Implementing the Scale vector-thread processor," ACM Trans. Design Automation of Electronic Systems, vol. 13, no. 3, pp. Art. 41:1-24, July 2008.
• S. Heo, R. Krashinsky, and K. Asanović, "Activity-sensitive flip-flop and latch selection for reduced energy," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1060-1064, Sep. 2007.
• J. Wawrzynek, D. A. Patterson, M. Oskin, S. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanović, "RAMP: Research Accelerator for Multiple Processors," IEEE Micro, vol. 27, no. 2, pp. 46-57, March 2007.
• K. C. Barr and K. Asanović, "Energy-aware lossless data compression," ACM Trans. Computer Systems, vol. 24, no. 3, pp. 250-291, Aug. 2006.
• C. S. Ananian, K. Asanović, B. C. Kuszmaul, C. E. Leiserson, and S. Lie, "Unbounded transactional memory," IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, pp. 59-69, Jan. 2006.
• H. Pan, K. Asanović, R. Cohn, and C. Luk, "Controlling program execution through binary instrumentation," ACM SIGARCH Computer Architecture News Special Issue: WBIA '05, vol. 33, no. 5, pp. 45-50, Dec. 2005.
• E. Witchel, J. Rhee, and K. Asanović, "Mondrix: Memory isolation for Linux using Mondriaan Memory Protection," ACM SIGOPS Operating Systems Review, vol. 39, no. 5, pp. 31-44, Dec. 2005.
• J. H. Tseng and K. Asanović, "A speculative control scheme for an energy-efficient banked register file," IEEE Trans. Computers, vol. 54, no. 6, pp. 741-751, June 2005.
• R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanović, "The vector-thread architecture," IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences 2004, vol. 24, no. 6, pp. 84-90, Nov. 2004.
• C. Kozyrakis, S. Perissakis, D. A. Patterson, T. Anderson, K. Asanović, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R. Thomas, N. Treuhaft, and K. A. Yelick, "Scalable Processors in the Billion Transistor: IRAM," Proceedings IEEE Computer, vol. 30, no. 9, Sep. 1997.
• J. Wawrzynek, K. Asanovic, B. Kingsbury, D. Johnson, J. Beck, and N. Morgan, "Spert-II: A vector microprocessor system," Computer, vol. 29, no. 3, pp. 79-86, March 1996.
• K. Asanović, N. Morgan, and J. Wawrzynek, "Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor," Journal of VLSI Signal Processing, vol. 6, pp. 33-44, 1993.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "Connectionist Network Supercomputer," International Journal of Neural Systems, vol. 4, no. 4, pp. 317-326, Dec. 1993.

Articles in conference proceedings

• S. Karandikar, A. N. Udipi, J. Choi, J. Whangbo, J. Zhao, S. Kanev, E. Lim, J. Alakuijala, V. Madduri, Y. S. Shao, B. Nikolic, K. Asanović, and P. Ranganathan, "CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems," in Proceedings of the 50th Annual International Symposium on Computer Architecture, ISCA '23, New York, NY, USA: Association for Computing Machinery, 2023.
• D. Lee, D. Kohlbrenner, S. Shinde, K. Asanović, and D. Song, "Keystone: An Open Framework for Architecting Trusted Execution Environments," in Proceedings of the Fifteenth European Conference on Computer Systems, EuroSys'20, 2020.
• S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra, Q. Huang, K. Kovacs, B. Nikolic, R. H. Katz, J. Bachrach, and K. Asanović, "FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud," in Proceedings of the 45th Annual International Symposium on Computer Architecture, ISCA '18, Piscataway, NJ, USA: IEEE Press, 2018, pp. 29--42.
• B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolic, "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC," in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 269-272.
• D. Kim, A. Izraelevitz, C. Celio, H. Kim, B. Zimmer, Y. Lee, J. Bachrach, and K. Asanović, "Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL," in ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016, pp. 128-139.
• M. Maas, E. Love, E. Stefanov, M. Tiwari, E. Shi, K. Asanović, J. D. Kubiatowicz, and D. Song, "Phantom: Practical oblivious computation in a secure processor," in Proceedings of the 2013 ACM SIGSAC conference on Computer \& communications security, 2013, pp. 311--324.
• H. Cook, M. Moreto, S. Bird, K. Dao, D. A. Patterson, and K. Asanović, "A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness," in Proceedings of the 40th Annual International Symposium on Computer Architecture, ACM, 2013, pp. 308-319.
• M. Maas, P. Reames, J. Morlan, K. Asanović, A. D. Joseph, and J. D. Kubiatowicz, "GPUs as an Opportunity for Offloading Garbage Collection," in Proceedings of the 2012 International Symposium on Memory Management, ISMM '12, New York, NY, USA: ACM, 2012, pp. 25--36.
• S. Beamer, K. Asanović, and D. A. Patterson, "Direction-optimizing breadth-first search," in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, IEEE Computer Society, 2012.
• M. Tiwari, P. Mohan, A. Osheroff, H. Alkaff, E. Love, E. Shi, D. Song, and K. Asanović, "Context-centric Security," in Proceedings of the 7th USENIX Workshop on Hot Topics in Security, HotSec'12, Usenix, 2012.
• Z. Tan, K. Asanović, and D. A. Patterson, "Datacenter-Scale Network Research on FPGAs," in Proceedings from Workshop on Exascale Evaluation and Research Techniques, 2011.
• Z. Tan, A. Waterman, H. Cook, S. Bird, K. Asanović, and D. A. Patterson, "A Case for FAME: FPGA Architecture Model Execution," in Proceedings of the 37th annual international symposium on Computer architecture, SCA '10, New York, NY: ACM, 2010, pp. 290-301.
• Z. Tan, A. Waterman, R. Avizienis, Y. Lee, H. Cook, D. A. Patterson, and K. Asanović, "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors," in DAC '10 Proceedings of the 47th Design Automation Conference, ACM, 2010, pp. 463-468.
• Z. Tan, K. Asanović, and D. A. Patterson, "An FPGA-based Simulator for Datacenter Networks," in Proccedings of Exascale Evaluation and Research Techniques Workshop, 2010.
• B. C. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting productivity and performance with selective embedded JIT specialization," in Proceedings First Workshop on Programming Models for Emerging Architectures, 2009.
• S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanovic, "Designing Multi-socket Systems Using Silicon Photonics," in Proceedings 23rd International Conference on Supercomputing, 2009.
• V. Stojanovic, A. Joshi, C. Batten, Y. Kwon, and K. Asanović, "Manycore processor networks with monolithic integrated CMOS," in 29th Conference on Lasers and Electro-Optics (CLEO'09), 2009.
• A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanovic, "Silicon-photonic clos networks for global on-chip communication," in NOCS '09: Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, Washington, DC, USA: IEEE Computer Society, 2009, pp. 124--133.
• A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamin, K. Asanović, and V. Stojanovic, "Silicon-Photonic Clos Networks for Global On-Chip Communication," in 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009.
• C. Jones, R. Liu, L. Meyerovich, K. Asanović, and R. Bodik, "Parallelizing the Web Browser," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
• R. Liu, K. Klues, S. Bird, S. Hofmeyr, K. Asanović, and J. D. Kubiatowicz, "Tessellation: Space-Time Partitioning in a Manycore Client OS," in First USENIX Workshop on Hot Topics in ParallelismH, 2009.
• H. Pan, B. Hindman, and K. Asanović, "Lithe: Enabling Efficient Composition of Parallel Libraries," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
• C. Batten, H. Aoki, and K. Asanović, "The case for malleable stream architectures," in Workshop on Streaming Systems, 2008.
• C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanović, "Building manycore processor-to-DRAM networks with monolithic silicon photonics," in Proc. 16th Annual IEEE Symp. on High-Performance Interconnects (HotI 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 21-30.
• Z. Tan, K. Asanović, and D. A. Patterson, "An FPGA host-multithreaded functional model for SPARC v8," in Proc. 3rd Workshop on Architectural Research Prototyping (WARP-2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 5 pg.
• J. W. Lee, M. C. Ng, and K. Asanović, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. 35th Intl. Symp. on Computer Architecture (ISCA 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 89-100.
• M. Hampton and K. Asanović, "Compiling for vector-thread architectures," in Proc. 6th Annual IEEE/ACM Intl. Symp. on Code Generation and Optimization (CGO-2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 205-215.
• K. Asanović, "Transactors for parallel hardware and software co-design (Invited Paper)," in Proc. 2007 IEEE Intl. High Level Design Validation and Test Workshop (HLDVT-2007), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 140-142.
• J. W. Lee, M. King, and K. Asanović, "Continual hashing for efficient fine-grain state inconsistency detection," in Proc. 25th IEEE Intl. Conf. on Computer Design (ICCD 2007), Piscataway, NJ: IEEE Press, 2007, pp. 33-40.
• R. Krashinsky, C. Batten, and K. Asanović, "The Scale Vector-Thread Processor (Winner, DAC/ISSCC Student Design Contest)," in Proc. 44th ACM/IEEE Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 3 pp..
• S. Crago, J. McMahon, C. Archer, K. Asanović, R. Chaung, K. Goolsbey, M. Hall, C. Kozyrakis, K. Olukotun, U. O'Reilly, R. Pancoast, V. Prasanna, R. Rabbah, S. Ward, and D. Yeung, "CEARCH: Cognition Enabled Architecture," in Proc. 10th Annual Workshop on High Performance Embedded Computing (HPEC 2006), Lexington, MA: MIT Lincoln Laboratory, 2006, pp. 2 pg.
• V. Paxson, K. Asanović, S. Dharmapurikar, J. W. Lockwood, R. Pang, R. Sommer, and N. Weaver, "Rethinking hardware support for network analysis and intrusion prevention," in Proc. 1st USENIX Workshop on Hot Topics in Security (HotSec '06), Berkeley, CA: USENIX Association, 2006, pp. 63-68.
• M. Hampton and K. Asanović, "Implementing virtual memory in a vector processor with software restart markers," in Proc. 20th Annual Intl. Conf. on Supercomputing (ICS 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 135-144.
• J. W. Lee and K. Asanović, "METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors," in Proc. 12th IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS 2006), S. Goddard and J. Liu, Eds., Los Alamitos, CA: IEEE Computer Society Press, 2006, pp. 135-147.
• R. F. Liu and K. Asanović, "Accelerating architectural exploration using canonical instruction segments," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software (IPASS '06), Piscataway, NJ: IEEE Press, 2006, pp. 13-24.
• K. C. Barr and K. Asanović, "Branch trace compression for snapshot-based simulation," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS '06), Piscataway, NJ: IEEE Press, 2006, pp. 25-35.
• G. Gibeling, A. Schultz, and K. Asanović, "The RAMP architecture & description language," in Proc. 2nd Workshop on Architecture Research Using FPGA Platforms (WARFP 2006), 2006, pp. 4 pp..
• S. Heo and K. Asanović, "Replacing global wires with an on-chip network: A power analysis," in Proc. 2005 Intl. Symp. on Low Power Electronics and Design (ISLPED '05), New York, NY: The Association for Computing Machinery, Inc., 2005, pp. 369-374.
• M. Zhang and K. Asanović, "Victim replication: Maximizing capacity while hiding wire delay in tiled CMPs," in Proc. 32nd Intl. Symp. on Computer Architecture (ISCA-32), Los Alamitos, CA: IEEE Computer Society, 2005, pp. 336-345.
• K. C. Barr, H. Pan, M. Zhang, and K. Asanović, "Accelerating multiprocessor simulation with a memory timestamp record," in Proc. IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS 2005), Piscataway, NJ: IEEE Computer Society, 2005, pp. 66-77.
• D. A. Patterson, K. Asanović, A. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft, and K. A. Yelick, "Intelligent RAM (IRAM): The Industrial Setting, Applications, and Architectures," in Proceedings of ICCD ‘97 International Conference on Computer Design: VLSI in Computers and Processors, ICCD, IEEE, 1997, pp. 2 - 7.
• J. Wawrzynek, K. Asanović, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan, "SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training," in Proceeding of NIPS 8, 1996, pp. 619-625.
• K. Asanović, J. Beck, B. Irissou, B. Kingsbury, N. Morgan, and J. Wawrzynek, "The T0 Vector Microprocessor," in Proceedings of Hot Chips VII, 1995.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "A supercomputer for neural computation," in Proc. 1994 IEEE Intl. Conf. on Neural Networks (ICNN '94), Vol. 1, Piscataway, NJ: IEEE Press, 1994, pp. 5-9.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "Development of a Connectionist Network Supercomputer," in Proceedings of Micro-Neuro 1993, 1993, pp. 253-262.
• J. Wawrzynek, K. Asanović, and N. Morgan, "The Design of a Neuro-Microprocessor," in Proceedings of IEEE Transactions on Neural Networks, Vol. 4, 1993, pp. 394-399.
• K. Asanović, J. Beck, B. Kingsubry, P. Kohn, N. Morgan, and J. Wawrzynek, "SPERT: A VLIW/SIMD Neuro-Microprocessor," in Proceedings of IJCNN '92, 1992, pp. II-577-582.
• K. Asanović, K. Schauser, D. A. Patterson, and E. Frank, "Evaluation of a Stall Cache: An Efficient Restricted On-chip Instruction Cache," in Proceedings of the Hawaii International Conference on System Sciences, HICSS, Vol. 1, 1992, pp. 405-415.

Technical Reports

• J. Zhao, D. Grubb, M. Rusch, T. Wei, K. Anderson, B. Nikolic, and K. Asanović, "The Saturn Microarchitecture Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2024-215, Dec. 2024.
• C. Celio, P. Chiu, B. Nikolic, D. A. Patterson, and K. Asanović, "BOOM v2: an open-source out-of-order RISC-V core," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-157, Sep. 2017.
• A. Waterman, Y. Lee, R. Avizienis, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.9.1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-161, Nov. 2016.
• C. Celio, D. Dabbelt, D. A. Patterson, and K. Asanović, "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-130, July 2016.
• A. Waterman, Y. Lee, R. Avizienis, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.9," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-129, July 2016.
• A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-118, May 2016.
• K. Asanović, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas, A. Magyar, H. Mao, M. Moreto, A. Ou, D. A. Patterson, B. Richards, C. Schmidt, S. Twigg, H. Vo, and A. Waterman, "The Rocket Chip Generator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, April 2016.
• Y. Lee, C. Schmidt, S. Karandikar, D. Dabbelt, A. Ou, and K. Asanović, "Hwacha Preliminary Evaluation Results, Version 3.8.1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-264, Dec. 2015.
• Y. Lee, A. Ou, C. Schmidt, S. Karandikar, H. Mao, and K. Asanović, "The Hwacha Microarchitecture Manual, Version 3.8.1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-263, Dec. 2015.
• Y. Lee, C. Schmidt, A. Ou, A. Waterman, and K. Asanović, "The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-262, Dec. 2015.
• A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Compressed Instruction Set Manual, Version 1.9," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-209, Nov. 2015.
• C. Celio, D. A. Patterson, and K. Asanović, "The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-167, June 2015.
• A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Compressed Instruction Set Manual, Version 1.7," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-157, May 2015.
• A. Waterman, Y. Lee, R. Avizienis, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-49, May 2015.
• K. Asanović and D. A. Patterson, "Instruction Sets Should Be Free: The Case For RISC-V," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146, Aug. 2014.
• G. Eads, J. Colmenares, S. Hofmeyr, S. Bird, D. Bartolini, D. Chou, B. Glutzman, K. Asanović, and J. D. Kubiatowicz, "Building an Adaptive Operating System for Predictability and Efficiency," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-137, July 2014.
• A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-54, May 2014.
• S. Beamer, A. Buluc ̧, K. Asanović, and D. A. Patterson, "Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2013-2, Jan. 2013.
• S. Beamer, K. Asanović, and D. A. Patterson, "Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2011-117, Nov. 2011.
• A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2011-62, May 2011.
• B. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2010-23, March 2010.
• S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic, and K. Asanović, "Re-architecting DRAM with Monolithically Integrated Silicon Photonics," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-179, Dec. 2009.
• H. Cook, K. Asanović, and D. A. Patterson, "Virtual Local Stores: Enabling Software-Managed Memory Hierarchies in Mainstream Computing Environments," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-131, Sep. 2009.
• S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanovic, "Designing Multi-socket Systems Using Silicon Photonics," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-9, Jan. 2009.
• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-23, March 2008.
• K. Asanović, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-183, Dec. 2006.
• J. Wawrzynek, M. Oskin, C. Kozyrakis, D. Chiou, D. A. Patterson, S. Lu, J. C. Hoe, and K. Asanović, "RAMP: A Research Accelerator for Multiple Processors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-158, Nov. 2006.
• Arvind, K. Asanović, D. Chiou, J. C. Hoe, C. Kozyrakis, S. Lu, M. Oskin, D. Patterson, J. Rabaey, and J. Wawrzynek, "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-05-1412, Sep. 2005.
• J. A. Bilmes, K. Asanović, C. Chin, and J. Demmel, "The PHiPAC v1.0 Matrix-Multiply Distribution," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-98-1020, Oct. 1998.
• K. Asanović and D. Johnson, "Torrent Architecture Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-97-930, Jan. 1997.
• K. Asanović and J. Beck, "T0 Engineering Data," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-97-931, Jan. 1997.
• K. Asanović, J. Beck, T. Callahan, J. A. Feldman, B. Irissou, B. Kingsbury, P. Kohn, J. Lazarro, N. Morgan, D. Stoutamire, and J. Wawrzynek, "CNS-1 Architecture Specification - A Connectionist Network Supercomputer," International Computer Science Institute, Tech. Rep. TR-93-021, 1993.
• K. Asanović, J. Beck, T. Callahan, J. Feldman, B. S. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire, and J. Wawrzynek, "CNS-1 Architecture Specification," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-747, 1993.
• K. Asanović, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek, "Development of a Connectionist Network Supercomputer," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-749, June 1993.
• B. Kingsbury, K. Asanović, B. Irissou, N. Morgan, and J. Wawrzynek, "Recent work in VLSI elements for digital implementations of Artificial Neural Networks," International Computer Science Institute, Tech. Rep. TR-91-074, 1991.
• K. Asanović, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek, "SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations," International Computer Science Institute, Tech. Rep. TR-91-072, 1991.
• K. Asanović and N. Morgan, "Experimental Determination of Precision Requirements for Back-propagation Training of Artificial Neural Networks," International Computer Science Institute, Tech. Rep. TR-91-036, 1991.
• K. E. Schauser, K. Asanović, D. A. Patterson, and E. H. Frank, "Evaluation of a "Stall" Cache: An Efficient Restricted On-chip Instruction Cache," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-91-641, July 1991.
• N. Morgan, K. Asanović, B. Kingsbury, and J. Wawrzynek, "Developments in Digital VLSI Design for Artificial Neural Networks," International Computer Science Institute, Tech. Rep. TR-090-065, 1990.

Patents

• S. C. Miller, M. M. Deneroff, C. F. Schimmel, L. Rudolph, C. E. Leiserson, B. C., and K. Asanović, "System and method for performing memory operations in a computing system," U.S. Patent 8,321,634. Nov. 2012.
• S. C. Miller, M. M. Deneroff, C. F. Schimmel, L. Rudolph, C. E. Leiserson, B. C. Kuszmaul, and K. Asanović, "System and method for performing memory operations in a computing system," U.S. Patent 7,925,839. April 2011.
• S. C. Miller, M. M. Deneroff, C. F. Schimmel, L. Rudolph, C. E. Leiserson, B. C. Kuszmaul, and K. Asanović, "System and method for performing memory operations in a computing system," U.S. Patent 7,398,359. July 2008.
• K. Asanović and E. J. Witchel, "System and technique for fine-grained computer memory protection," U.S. Patent 7,287,140. Oct. 2007.
• K. Asanović, "Vector processing system with multi-operation, run-time reconfigurable pipelines," U.S. Patent 5,805,875. Sep. 1998.

Ph.D. Theses

• H. Mao, "Designing New Memory Systems for Next-Generation Data Centers," R. H. Katz and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2022-240, Dec. 2022.
• A. Izraelevitz, "Unlocking Design Reuse with Hardware Compiler Frameworks," J. Bachrach, K. Asanović, S. Schleicher, and J. Ragan-Kelley, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-168, Dec. 2019.
• B. Keller, "Energy-Efficient System Design Through Adaptive Voltage Scaling," B. Nikolic, K. Asanović, and D. Callaway, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-146, Dec. 2019.
• H. Cook, "Productive Design of Extensible On-Chip Memory Hierarchies," K. Asanović and D. A. Patterson, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-89, May 2016.
• K. Asanović, "Vector Microprocessors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-98-1014, 1998.

Masters Reports

• J. Whangbo, K. Asanović, and B. Nikolic, "FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2024-220, Dec. 2024.
• A. Amid, "Nested-Parallelism PageRank on RISC-V Vector Multi-Processors," B. Nikolic and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-6, April 2019.
• S. Karandikar, "FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud," K. Asanović and R. H. Katz, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2018-154, Dec. 2018.
• H. Mao, "Hardware Acceleration for Memory to Memory Copies," R. H. Katz and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-2, Jan. 2017.
• A. Ou, "Mixed Precision Vector Processors," K. Asanović and V. Stojanovic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-265, Dec. 2015.
• B. Keller, "Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency," B. Nikolic and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-257, Dec. 2015.
• B. Zimmer, B. Nikolic, and K. Asanović, "Resilient Design Methodology for Energy-Efficient SRAM," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2013-37, May 2013.
• S. Beamer, "Designing Multisocket Systems with Silicon Photonics," K. Asanović and D. A. Patterson, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-189, Dec. 2009.