Master's Theses & Technical Reports - Krste Asanović

M.S. | 5th Year M.S.

M.S.

RingBOOM: An Implementation of a Novel High-Performance Banked Microarchitecture
Benjamin Korpan [2020]

Nested-Parallelism PageRank on RISC-V Vector Multi-Processors
Alon Amid [2019]

A Hardware Accelerator for Computing an Exact Dot Product
Jack Koenig [2018]

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
Sagar Karandikar [2018]

PLSI: A Portable VLSI Flow
Daniel Dabbelt [2017]

Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL
Donggyu Kim [2016]

Mixed Precision Vector Processors
Albert Ou [2015]

Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency
Ben Keller [2015]

Ressort: An Auto-Tuning Framework for Parallel Shuffle Kernels
Eric Love [2015]

PHANTOM: Practical Oblivious Computation in a Secure Processor
Martin Maas [2014]

Resilient Design Methodology for Energy-Efficient SRAM
Brian Zimmer [2012]

Efficient VLSI Implementations of Vector-Thread Architectures
Yunsup Lee [2011]

Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed
Andrew Waterman [2011]

The Case for User-Level Preemptive Scheduling to Support Multi-Rate Audio Applications for Multi-Core Processors
Rimas Avizienis [2011]

Designing Multisocket Systems with Silicon Photonics
Scott Beamer [2009]

5th Year M.S.

Reduce Static Code Size and Improve RISC-V Compression
Peijie Li [2019]

Automatic Functional Datapath Optimization
Wenyu Tang [2014]

Hardware Construction in Chisel
Huy Vo [2013]

L2 Cache to Off-chip Memory Networks for Chip Multiprocessor
Carrell Killebrew [2008]